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<a href="#nested-classes">Data Structures</a> &#124;
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> driver instance data.  <a href="struct_x_axi_dma.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axi_dma___config.html">XAxiDma_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The configuration structure for AXI DMA engine.  <a href="struct_x_axi_dma___config.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Container structure for descriptor storage control.  <a href="struct_x_axi_dma___bd_ring.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga9d91f29c6dc41f2106e097f1f9957a6e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">XAxiDma_GetTxRing</a>(InstancePtr)&#160;&#160;&#160;(&amp;((InstancePtr)-&gt;TxBdRing))</td></tr>
<tr class="memdesc:ga9d91f29c6dc41f2106e097f1f9957a6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get Transmit (Tx) Ring ptr.  <a href="#ga9d91f29c6dc41f2106e097f1f9957a6e">More...</a><br /></td></tr>
<tr class="separator:ga9d91f29c6dc41f2106e097f1f9957a6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6373ac3baa5365607f6727f4e2ece7a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga6373ac3baa5365607f6727f4e2ece7a5">XAxiDma_GetRxRing</a>(InstancePtr)&#160;&#160;&#160;(&amp;((InstancePtr)-&gt;RxBdRing[0]))</td></tr>
<tr class="memdesc:ga6373ac3baa5365607f6727f4e2ece7a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get Receive (Rx) Ring ptr.  <a href="#ga6373ac3baa5365607f6727f4e2ece7a5">More...</a><br /></td></tr>
<tr class="separator:ga6373ac3baa5365607f6727f4e2ece7a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf03e87b58cf2f9800e6260fda3745631"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaf03e87b58cf2f9800e6260fda3745631">XAxiDma_GetRxIndexRing</a>(InstancePtr,  RingIndex)&#160;&#160;&#160;(&amp;((InstancePtr)-&gt;RxBdRing[RingIndex]))</td></tr>
<tr class="memdesc:gaf03e87b58cf2f9800e6260fda3745631"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get Receive (Rx) Ring ptr of a Index.  <a href="#gaf03e87b58cf2f9800e6260fda3745631">More...</a><br /></td></tr>
<tr class="separator:gaf03e87b58cf2f9800e6260fda3745631"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18dd03026dd6c0ebd13526116c09ccae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">XAxiDma_HasSg</a>(InstancePtr)&#160;&#160;&#160;((InstancePtr)-&gt;HasSg) ? TRUE : FALSE</td></tr>
<tr class="memdesc:ga18dd03026dd6c0ebd13526116c09ccae"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function checks whether system is configured as Simple or Scatter Gather mode.  <a href="#ga18dd03026dd6c0ebd13526116c09ccae">More...</a><br /></td></tr>
<tr class="separator:ga18dd03026dd6c0ebd13526116c09ccae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadac28afa26e2cb55bdada1ee3c016c52"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadac28afa26e2cb55bdada1ee3c016c52">XAxiDma_IntrEnable</a>(InstancePtr,  Mask,  Direction)</td></tr>
<tr class="memdesc:gadac28afa26e2cb55bdada1ee3c016c52"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables interrupts specified by the Mask in specified direction, Interrupts that are not in the mask are not affected.  <a href="#gadac28afa26e2cb55bdada1ee3c016c52">More...</a><br /></td></tr>
<tr class="separator:gadac28afa26e2cb55bdada1ee3c016c52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadba63ad7c0a784d569736a8d1eb7c367"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadba63ad7c0a784d569736a8d1eb7c367">XAxiDma_IntrGetEnabled</a>(InstancePtr,  Direction)</td></tr>
<tr class="memdesc:gadba63ad7c0a784d569736a8d1eb7c367"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the mask for the interrupts that are currently enabled.  <a href="#gadba63ad7c0a784d569736a8d1eb7c367">More...</a><br /></td></tr>
<tr class="separator:gadba63ad7c0a784d569736a8d1eb7c367"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1936b497c0fa61d326807e5ed8dd572b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga1936b497c0fa61d326807e5ed8dd572b">XAxiDma_IntrDisable</a>(InstancePtr,  Mask,  Direction)</td></tr>
<tr class="memdesc:ga1936b497c0fa61d326807e5ed8dd572b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function disables interrupts specified by the Mask.  <a href="#ga1936b497c0fa61d326807e5ed8dd572b">More...</a><br /></td></tr>
<tr class="separator:ga1936b497c0fa61d326807e5ed8dd572b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6a0eb17bcfcaf3331e01855d302f5f0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga6a0eb17bcfcaf3331e01855d302f5f0e">XAxiDma_IntrGetIrq</a>(InstancePtr,  Direction)</td></tr>
<tr class="memdesc:ga6a0eb17bcfcaf3331e01855d302f5f0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the interrupts that are asserted.  <a href="#ga6a0eb17bcfcaf3331e01855d302f5f0e">More...</a><br /></td></tr>
<tr class="separator:ga6a0eb17bcfcaf3331e01855d302f5f0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ff0d2e5b50846e4b6a2d683283c10d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga9ff0d2e5b50846e4b6a2d683283c10d5">XAxiDma_IntrAckIrq</a>(InstancePtr,  Mask,  Direction)</td></tr>
<tr class="memdesc:ga9ff0d2e5b50846e4b6a2d683283c10d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function acknowledges the interrupts that are specified in Mask.  <a href="#ga9ff0d2e5b50846e4b6a2d683283c10d5">More...</a><br /></td></tr>
<tr class="separator:ga9ff0d2e5b50846e4b6a2d683283c10d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa738ffd392c7ae1e844fab340ba50fee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>(BaseAddress,  Offset)&#160;&#160;&#160;(*(u32 *)(((void *)(UINTPTR)(BaseAddress)) + (u32)(Offset)))</td></tr>
<tr class="memdesc:gaa738ffd392c7ae1e844fab340ba50fee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the given Buffer Descriptor word.  <a href="#gaa738ffd392c7ae1e844fab340ba50fee">More...</a><br /></td></tr>
<tr class="separator:gaa738ffd392c7ae1e844fab340ba50fee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab3b7d771208c01701b35bce165332a9f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>(BaseAddress,  Offset,  Data)&#160;&#160;&#160;(*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data)</td></tr>
<tr class="memdesc:gab3b7d771208c01701b35bce165332a9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write the given Buffer Descriptor word.  <a href="#gab3b7d771208c01701b35bce165332a9f">More...</a><br /></td></tr>
<tr class="separator:gab3b7d771208c01701b35bce165332a9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga273953f607ecfa92d879c4ee3660f954"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga273953f607ecfa92d879c4ee3660f954">XAxiDma_BdWrite64</a>(BaseAddress,  Offset,  Data)&#160;&#160;&#160;(*(u64 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u64)(Data)</td></tr>
<tr class="memdesc:ga273953f607ecfa92d879c4ee3660f954"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write the given Buffer Descriptor word.  <a href="#ga273953f607ecfa92d879c4ee3660f954">More...</a><br /></td></tr>
<tr class="separator:ga273953f607ecfa92d879c4ee3660f954"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga86ffdcf7973d9648a0f4a4079f5d6e92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga86ffdcf7973d9648a0f4a4079f5d6e92">XAxiDma_BdClear</a>(BdPtr)</td></tr>
<tr class="memdesc:ga86ffdcf7973d9648a0f4a4079f5d6e92"><td class="mdescLeft">&#160;</td><td class="mdescRight">Zero out BD specific fields.  <a href="#ga86ffdcf7973d9648a0f4a4079f5d6e92">More...</a><br /></td></tr>
<tr class="separator:ga86ffdcf7973d9648a0f4a4079f5d6e92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga495e780d704ecf548d3536b3bb8961a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga495e780d704ecf548d3536b3bb8961a5">XAxiDma_BdGetCtrl</a>(BdPtr)</td></tr>
<tr class="memdesc:ga495e780d704ecf548d3536b3bb8961a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the control bits for the BD.  <a href="#ga495e780d704ecf548d3536b3bb8961a5">More...</a><br /></td></tr>
<tr class="separator:ga495e780d704ecf548d3536b3bb8961a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a0271e5255b139cc63e08e46b9c473a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga8a0271e5255b139cc63e08e46b9c473a">XAxiDma_BdGetSts</a>(BdPtr)</td></tr>
<tr class="memdesc:ga8a0271e5255b139cc63e08e46b9c473a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the status of a BD.  <a href="#ga8a0271e5255b139cc63e08e46b9c473a">More...</a><br /></td></tr>
<tr class="separator:ga8a0271e5255b139cc63e08e46b9c473a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadaf226acada2c1d857d29205ce4c2a58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadaf226acada2c1d857d29205ce4c2a58">XAxiDma_BdGetLength</a>(BdPtr,  LengthMask)</td></tr>
<tr class="memdesc:gadaf226acada2c1d857d29205ce4c2a58"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the length field value from the given BD.  <a href="#gadaf226acada2c1d857d29205ce4c2a58">More...</a><br /></td></tr>
<tr class="separator:gadaf226acada2c1d857d29205ce4c2a58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d935ef5d41f72d0d57a15aaf5928062"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga3d935ef5d41f72d0d57a15aaf5928062">XAxiDma_BdSetId</a>(BdPtr,  Id)&#160;&#160;&#160;(<a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>((BdPtr), <a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">XAXIDMA_BD_ID_OFFSET</a>, (u32)(Id)))</td></tr>
<tr class="memdesc:ga3d935ef5d41f72d0d57a15aaf5928062"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the ID field of the given BD.  <a href="#ga3d935ef5d41f72d0d57a15aaf5928062">More...</a><br /></td></tr>
<tr class="separator:ga3d935ef5d41f72d0d57a15aaf5928062"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3f333d78d115724bfcac84746d8cfa6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaf3f333d78d115724bfcac84746d8cfa6">XAxiDma_BdGetId</a>(BdPtr)&#160;&#160;&#160;(<a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">XAXIDMA_BD_ID_OFFSET</a>))</td></tr>
<tr class="memdesc:gaf3f333d78d115724bfcac84746d8cfa6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId.  <a href="#gaf3f333d78d115724bfcac84746d8cfa6">More...</a><br /></td></tr>
<tr class="separator:gaf3f333d78d115724bfcac84746d8cfa6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab7295cfd7835998272435a39b656bf1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gab7295cfd7835998272435a39b656bf1f">XAxiDma_BdGetBufAddr</a>(BdPtr)&#160;&#160;&#160;(<a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">XAXIDMA_BD_BUFA_OFFSET</a>))</td></tr>
<tr class="memdesc:gab7295cfd7835998272435a39b656bf1f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the BD's buffer address.  <a href="#gab7295cfd7835998272435a39b656bf1f">More...</a><br /></td></tr>
<tr class="separator:gab7295cfd7835998272435a39b656bf1f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga844fc6b60315598387d17c8148a891e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga844fc6b60315598387d17c8148a891e4">XAxiDma_BdHwCompleted</a>(BdPtr)</td></tr>
<tr class="memdesc:ga844fc6b60315598387d17c8148a891e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check whether a BD has completed in hardware.  <a href="#ga844fc6b60315598387d17c8148a891e4">More...</a><br /></td></tr>
<tr class="separator:ga844fc6b60315598387d17c8148a891e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaae88a4ef129d6100fd087f7693186d80"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaae88a4ef129d6100fd087f7693186d80">XAxiDma_BdGetActualLength</a>(BdPtr,  LengthMask)</td></tr>
<tr class="memdesc:gaae88a4ef129d6100fd087f7693186d80"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the actual transfer length of a BD.  <a href="#gaae88a4ef129d6100fd087f7693186d80">More...</a><br /></td></tr>
<tr class="separator:gaae88a4ef129d6100fd087f7693186d80"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa5bc321894b77ca6194c867018d9fe12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaa5bc321894b77ca6194c867018d9fe12">XAxiDma_BdSetTId</a>(BdPtr,  TId)</td></tr>
<tr class="memdesc:gaa5bc321894b77ca6194c867018d9fe12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the TID field of the TX BD.  <a href="#gaa5bc321894b77ca6194c867018d9fe12">More...</a><br /></td></tr>
<tr class="separator:gaa5bc321894b77ca6194c867018d9fe12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac14fa76311fd7e5fb59b81fd9e251f62"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac14fa76311fd7e5fb59b81fd9e251f62">XAxiDma_BdGetTId</a>(BdPtr)</td></tr>
<tr class="memdesc:gac14fa76311fd7e5fb59b81fd9e251f62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId.  <a href="#gac14fa76311fd7e5fb59b81fd9e251f62">More...</a><br /></td></tr>
<tr class="separator:gac14fa76311fd7e5fb59b81fd9e251f62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5f9b3088c4e16c7f5584610a43b17462"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga5f9b3088c4e16c7f5584610a43b17462">XAxiDma_BdSetTDest</a>(BdPtr,  TDest)</td></tr>
<tr class="memdesc:ga5f9b3088c4e16c7f5584610a43b17462"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the TDEST field of the TX BD.  <a href="#ga5f9b3088c4e16c7f5584610a43b17462">More...</a><br /></td></tr>
<tr class="separator:ga5f9b3088c4e16c7f5584610a43b17462"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c1e3dd04821568424ffc77caf11a851"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga8c1e3dd04821568424ffc77caf11a851">XAxiDma_BdGetTDest</a>(BdPtr)</td></tr>
<tr class="memdesc:ga8c1e3dd04821568424ffc77caf11a851"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the TDest field of the RX BD previously set with i XAxiDma_BdSetTDest.  <a href="#ga8c1e3dd04821568424ffc77caf11a851">More...</a><br /></td></tr>
<tr class="separator:ga8c1e3dd04821568424ffc77caf11a851"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf41c0ebe00870b6cdd34e46698e081b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gacf41c0ebe00870b6cdd34e46698e081b">XAxiDma_BdSetTUser</a>(BdPtr,  TUser)</td></tr>
<tr class="memdesc:gacf41c0ebe00870b6cdd34e46698e081b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the TUSER field of the TX BD.  <a href="#gacf41c0ebe00870b6cdd34e46698e081b">More...</a><br /></td></tr>
<tr class="separator:gacf41c0ebe00870b6cdd34e46698e081b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a2f9668058b7e4cdc89dffcce6086d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga7a2f9668058b7e4cdc89dffcce6086d3">XAxiDma_BdGetTUser</a>(BdPtr)</td></tr>
<tr class="memdesc:ga7a2f9668058b7e4cdc89dffcce6086d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the TUSER field of the RX BD previously set with XAxiDma_BdSetTUser.  <a href="#ga7a2f9668058b7e4cdc89dffcce6086d3">More...</a><br /></td></tr>
<tr class="separator:ga7a2f9668058b7e4cdc89dffcce6086d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7d8a383cd6d5aff6ee36c3a3db20cbf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac7d8a383cd6d5aff6ee36c3a3db20cbf">XAxiDma_BdSetARCache</a>(BdPtr,  ARCache)</td></tr>
<tr class="memdesc:gac7d8a383cd6d5aff6ee36c3a3db20cbf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the ARCACHE field of the given BD.  <a href="#gac7d8a383cd6d5aff6ee36c3a3db20cbf">More...</a><br /></td></tr>
<tr class="separator:gac7d8a383cd6d5aff6ee36c3a3db20cbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa5f7ba67cbbb678662e4b5d36c63d16e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaa5f7ba67cbbb678662e4b5d36c63d16e">XAxiDma_BdGetARCache</a>(BdPtr)</td></tr>
<tr class="memdesc:gaa5f7ba67cbbb678662e4b5d36c63d16e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the ARCACHE field of the given BD previously set with XAxiDma_BdSetARCache.  <a href="#gaa5f7ba67cbbb678662e4b5d36c63d16e">More...</a><br /></td></tr>
<tr class="separator:gaa5f7ba67cbbb678662e4b5d36c63d16e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae89253197f1aef6582d5cda3e49f8ead"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gae89253197f1aef6582d5cda3e49f8ead">XAxiDma_BdSetARUser</a>(BdPtr,  ARUser)</td></tr>
<tr class="memdesc:gae89253197f1aef6582d5cda3e49f8ead"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the ARUSER field of the given BD.  <a href="#gae89253197f1aef6582d5cda3e49f8ead">More...</a><br /></td></tr>
<tr class="separator:gae89253197f1aef6582d5cda3e49f8ead"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72d1616af8d996f12db78473a75b54b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga72d1616af8d996f12db78473a75b54b6">XAxiDma_BdGetARUser</a>(BdPtr)</td></tr>
<tr class="memdesc:ga72d1616af8d996f12db78473a75b54b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the ARUSER field of the given BD previously set with XAxiDma_BdSetARUser.  <a href="#ga72d1616af8d996f12db78473a75b54b6">More...</a><br /></td></tr>
<tr class="separator:ga72d1616af8d996f12db78473a75b54b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga58961be41e3c0bc2694444bfe37b6c27"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga58961be41e3c0bc2694444bfe37b6c27">XAxiDma_BdSetStride</a>(BdPtr,  Stride)</td></tr>
<tr class="memdesc:ga58961be41e3c0bc2694444bfe37b6c27"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the STRIDE field of the given BD.  <a href="#ga58961be41e3c0bc2694444bfe37b6c27">More...</a><br /></td></tr>
<tr class="separator:ga58961be41e3c0bc2694444bfe37b6c27"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29a75b8f1de16a347544e37b48d8129c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga29a75b8f1de16a347544e37b48d8129c">XAxiDma_BdGetStride</a>(BdPtr)</td></tr>
<tr class="memdesc:ga29a75b8f1de16a347544e37b48d8129c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetStride.  <a href="#ga29a75b8f1de16a347544e37b48d8129c">More...</a><br /></td></tr>
<tr class="separator:ga29a75b8f1de16a347544e37b48d8129c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga383b2c0667bf5bafa22922168895bd5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga383b2c0667bf5bafa22922168895bd5e">XAxiDma_BdSetVSize</a>(BdPtr,  VSize)</td></tr>
<tr class="memdesc:ga383b2c0667bf5bafa22922168895bd5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the VSIZE field of the given BD.  <a href="#ga383b2c0667bf5bafa22922168895bd5e">More...</a><br /></td></tr>
<tr class="separator:ga383b2c0667bf5bafa22922168895bd5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9f48ceb5b30d66bab23337edc35d2fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gad9f48ceb5b30d66bab23337edc35d2fe">XAxiDma_BdGetVSize</a>(BdPtr)</td></tr>
<tr class="memdesc:gad9f48ceb5b30d66bab23337edc35d2fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetVSize.  <a href="#gad9f48ceb5b30d66bab23337edc35d2fe">More...</a><br /></td></tr>
<tr class="separator:gad9f48ceb5b30d66bab23337edc35d2fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c87fcb74fe669b5998e53d0a4b35127"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga5c87fcb74fe669b5998e53d0a4b35127">XAxiDma_BdRingCntCalc</a>(Alignment,  Bytes)&#160;&#160;&#160;(uint32_t)((Bytes)/((sizeof(<a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a>)+((Alignment)-1))&amp;~((Alignment)-1)))</td></tr>
<tr class="memdesc:ga5c87fcb74fe669b5998e53d0a4b35127"><td class="mdescLeft">&#160;</td><td class="mdescRight">Use this macro at initialization time to determine how many BDs will fit within the given memory constraints.  <a href="#ga5c87fcb74fe669b5998e53d0a4b35127">More...</a><br /></td></tr>
<tr class="separator:ga5c87fcb74fe669b5998e53d0a4b35127"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6899085c400b8f453381b305ac5521d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga6899085c400b8f453381b305ac5521d9">XAxiDma_BdRingMemCalc</a>(Alignment,  NumBd)&#160;&#160;&#160;(int)((sizeof(<a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a>)+((Alignment)-1)) &amp; ~((Alignment)-1))*(NumBd)</td></tr>
<tr class="memdesc:ga6899085c400b8f453381b305ac5521d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Use this macro at initialization time to determine how many bytes of memory are required to contain a given number of BDs at a given alignment.  <a href="#ga6899085c400b8f453381b305ac5521d9">More...</a><br /></td></tr>
<tr class="separator:ga6899085c400b8f453381b305ac5521d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac62389e25e6775026cf1be6c383e665b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac62389e25e6775026cf1be6c383e665b">XAxiDma_BdRingGetCnt</a>(RingPtr)&#160;&#160;&#160;((RingPtr)-&gt;AllCnt)</td></tr>
<tr class="memdesc:gac62389e25e6775026cf1be6c383e665b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Return the total number of BDs allocated by this channel with <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>.  <a href="#gac62389e25e6775026cf1be6c383e665b">More...</a><br /></td></tr>
<tr class="separator:gac62389e25e6775026cf1be6c383e665b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga415cf0c379fef0104f9f52881ead13a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga415cf0c379fef0104f9f52881ead13a7">XAxiDma_BdRingGetFreeCnt</a>(RingPtr)&#160;&#160;&#160;((RingPtr)-&gt;FreeCnt)</td></tr>
<tr class="memdesc:ga415cf0c379fef0104f9f52881ead13a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Return the number of BDs allocatable with <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a> for pre- processing.  <a href="#ga415cf0c379fef0104f9f52881ead13a7">More...</a><br /></td></tr>
<tr class="separator:ga415cf0c379fef0104f9f52881ead13a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d79253861939c76e6d440ecde2b6edd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga0d79253861939c76e6d440ecde2b6edd">XAxiDma_BdRingSnapShotCurrBd</a>(RingPtr)</td></tr>
<tr class="memdesc:ga0d79253861939c76e6d440ecde2b6edd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Snap shot the latest BD a BD ring is processing.  <a href="#ga0d79253861939c76e6d440ecde2b6edd">More...</a><br /></td></tr>
<tr class="separator:ga0d79253861939c76e6d440ecde2b6edd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd32e45591597a4bfa84b66dffc98913"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadd32e45591597a4bfa84b66dffc98913">XAxiDma_BdRingGetCurrBd</a>(RingPtr)</td></tr>
<tr class="memdesc:gadd32e45591597a4bfa84b66dffc98913"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the BD a BD ring is processing.  <a href="#gadd32e45591597a4bfa84b66dffc98913">More...</a><br /></td></tr>
<tr class="separator:gadd32e45591597a4bfa84b66dffc98913"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4b7e75d1acf86428bd79fcd0d1c13745"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745">XAxiDma_BdRingNext</a>(RingPtr,  BdPtr)</td></tr>
<tr class="memdesc:ga4b7e75d1acf86428bd79fcd0d1c13745"><td class="mdescLeft">&#160;</td><td class="mdescRight">Return the next BD in the ring.  <a href="#ga4b7e75d1acf86428bd79fcd0d1c13745">More...</a><br /></td></tr>
<tr class="separator:ga4b7e75d1acf86428bd79fcd0d1c13745"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga86c6d4b9c4f8766634d46a3078eadc8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga86c6d4b9c4f8766634d46a3078eadc8a">XAxiDma_BdRingPrev</a>(RingPtr,  BdPtr)</td></tr>
<tr class="memdesc:ga86c6d4b9c4f8766634d46a3078eadc8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Return the previous BD in the ring.  <a href="#ga86c6d4b9c4f8766634d46a3078eadc8a">More...</a><br /></td></tr>
<tr class="separator:ga86c6d4b9c4f8766634d46a3078eadc8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga740fa349c7811de2b7bae5cf83eb445e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga740fa349c7811de2b7bae5cf83eb445e">XAxiDma_BdRingGetSr</a>(RingPtr)&#160;&#160;&#160;<a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>)</td></tr>
<tr class="memdesc:ga740fa349c7811de2b7bae5cf83eb445e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the contents of the channel status register.  <a href="#ga740fa349c7811de2b7bae5cf83eb445e">More...</a><br /></td></tr>
<tr class="separator:ga740fa349c7811de2b7bae5cf83eb445e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga24cd47cdbfac0813e0d9caf966a1a3d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga24cd47cdbfac0813e0d9caf966a1a3d2">XAxiDma_BdRingGetError</a>(RingPtr)</td></tr>
<tr class="memdesc:ga24cd47cdbfac0813e0d9caf966a1a3d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get error bits of a DMA channel.  <a href="#ga24cd47cdbfac0813e0d9caf966a1a3d2">More...</a><br /></td></tr>
<tr class="separator:ga24cd47cdbfac0813e0d9caf966a1a3d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga766bed2454969636d827fb79faeeee97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">XAxiDma_BdRingHwIsStarted</a>(RingPtr)</td></tr>
<tr class="memdesc:ga766bed2454969636d827fb79faeeee97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check whether a DMA channel is started, meaning the channel is not halted.  <a href="#ga766bed2454969636d827fb79faeeee97">More...</a><br /></td></tr>
<tr class="separator:ga766bed2454969636d827fb79faeeee97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf7c291190c92ce93d72f95c5b04ef1d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaf7c291190c92ce93d72f95c5b04ef1d4">XAxiDma_BdRingBusy</a>(RingPtr)</td></tr>
<tr class="memdesc:gaf7c291190c92ce93d72f95c5b04ef1d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check if the current DMA channel is busy with a DMA operation.  <a href="#gaf7c291190c92ce93d72f95c5b04ef1d4">More...</a><br /></td></tr>
<tr class="separator:gaf7c291190c92ce93d72f95c5b04ef1d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2518030938ab80081f6896fc5589682c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga2518030938ab80081f6896fc5589682c">XAxiDma_BdRingIntEnable</a>(RingPtr,  Mask)</td></tr>
<tr class="memdesc:ga2518030938ab80081f6896fc5589682c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set interrupt enable bits for a channel.  <a href="#ga2518030938ab80081f6896fc5589682c">More...</a><br /></td></tr>
<tr class="separator:ga2518030938ab80081f6896fc5589682c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadbb17169213d8af8b50e6dee7f7b6d8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadbb17169213d8af8b50e6dee7f7b6d8b">XAxiDma_BdRingIntGetEnabled</a>(RingPtr)</td></tr>
<tr class="memdesc:gadbb17169213d8af8b50e6dee7f7b6d8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get enabled interrupts of a channel.  <a href="#gadbb17169213d8af8b50e6dee7f7b6d8b">More...</a><br /></td></tr>
<tr class="separator:gadbb17169213d8af8b50e6dee7f7b6d8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0269e07693c731cf7721c6f19f8eb69b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga0269e07693c731cf7721c6f19f8eb69b">XAxiDma_BdRingIntDisable</a>(RingPtr,  Mask)</td></tr>
<tr class="memdesc:ga0269e07693c731cf7721c6f19f8eb69b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear interrupt enable bits for a channel.  <a href="#ga0269e07693c731cf7721c6f19f8eb69b">More...</a><br /></td></tr>
<tr class="separator:ga0269e07693c731cf7721c6f19f8eb69b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a9d2103e6d09fc3850b34a6386dc803"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga7a9d2103e6d09fc3850b34a6386dc803">XAxiDma_BdRingGetIrq</a>(RingPtr)</td></tr>
<tr class="memdesc:ga7a9d2103e6d09fc3850b34a6386dc803"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET.  <a href="#ga7a9d2103e6d09fc3850b34a6386dc803">More...</a><br /></td></tr>
<tr class="separator:ga7a9d2103e6d09fc3850b34a6386dc803"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e782e3715c1d2dd03e5d03434f47319"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga9e782e3715c1d2dd03e5d03434f47319">XAxiDma_BdRingAckIrq</a>(RingPtr,  Mask)</td></tr>
<tr class="memdesc:ga9e782e3715c1d2dd03e5d03434f47319"><td class="mdescLeft">&#160;</td><td class="mdescRight">Acknowledge asserted interrupts.  <a href="#ga9e782e3715c1d2dd03e5d03434f47319">More...</a><br /></td></tr>
<tr class="separator:ga9e782e3715c1d2dd03e5d03434f47319"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga170ce0e12eb12686a03e006610e2acd2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga170ce0e12eb12686a03e006610e2acd2">XAXIDMA_DESC_LSB_MASK</a>&#160;&#160;&#160;(0xFFFFFFC0U)</td></tr>
<tr class="memdesc:ga170ce0e12eb12686a03e006610e2acd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">LSB Address mask.  <a href="#ga170ce0e12eb12686a03e006610e2acd2">More...</a><br /></td></tr>
<tr class="separator:ga170ce0e12eb12686a03e006610e2acd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:gac08fe7cb6508a133a7ef036bba7df5b5"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_axi_dma.html">XAxiDma</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac08fe7cb6508a133a7ef036bba7df5b5">XAxiDma</a></td></tr>
<tr class="memdesc:gac08fe7cb6508a133a7ef036bba7df5b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> driver instance data.  <a href="#gac08fe7cb6508a133a7ef036bba7df5b5">More...</a><br /></td></tr>
<tr class="separator:gac08fe7cb6508a133a7ef036bba7df5b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5faf4d844b10fc577f3a75a170f11867"><td class="memItemLeft" align="right" valign="top">typedef u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a>[<a class="el" href="group__axidma__v9__0.html#ga751f6662ab9baed908685eef30d322b8">XAXIDMA_BD_NUM_WORDS</a>]</td></tr>
<tr class="memdesc:ga5faf4d844b10fc577f3a75a170f11867"><td class="mdescLeft">&#160;</td><td class="mdescRight">The XAxiDma_Bd is the type for a buffer descriptor (BD).  <a href="#ga5faf4d844b10fc577f3a75a170f11867">More...</a><br /></td></tr>
<tr class="separator:ga5faf4d844b10fc577f3a75a170f11867"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga8026e76c90d891d21c9c355ff776cb77"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize</a> (<a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *InstancePtr, <a class="el" href="struct_x_axi_dma___config.html">XAxiDma_Config</a> *Config)</td></tr>
<tr class="memdesc:ga8026e76c90d891d21c9c355ff776cb77"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initializes a DMA engine.  <a href="#ga8026e76c90d891d21c9c355ff776cb77">More...</a><br /></td></tr>
<tr class="separator:ga8026e76c90d891d21c9c355ff776cb77"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b7d1248ef065915fd8c9e8d5e00640f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset</a> (<a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga5b7d1248ef065915fd8c9e8d5e00640f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset both TX and RX channels of a DMA engine.  <a href="#ga5b7d1248ef065915fd8c9e8d5e00640f">More...</a><br /></td></tr>
<tr class="separator:ga5b7d1248ef065915fd8c9e8d5e00640f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf73e1329e40c8ac1ae47a7d9c104af75"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone</a> (<a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaf73e1329e40c8ac1ae47a7d9c104af75"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check whether reset is done.  <a href="#gaf73e1329e40c8ac1ae47a7d9c104af75">More...</a><br /></td></tr>
<tr class="separator:gaf73e1329e40c8ac1ae47a7d9c104af75"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb572b623215a7df62b1e0468e3bd68c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause</a> (<a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *InstancePtr)</td></tr>
<tr class="memdesc:gadb572b623215a7df62b1e0468e3bd68c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pause DMA transactions on both channels.  <a href="#gadb572b623215a7df62b1e0468e3bd68c">More...</a><br /></td></tr>
<tr class="separator:gadb572b623215a7df62b1e0468e3bd68c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga847cd9a0255fcb444bce58b945de8574"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574">XAxiDma_Resume</a> (<a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga847cd9a0255fcb444bce58b945de8574"><td class="mdescLeft">&#160;</td><td class="mdescRight">Resume DMA transactions on both channels.  <a href="#ga847cd9a0255fcb444bce58b945de8574">More...</a><br /></td></tr>
<tr class="separator:ga847cd9a0255fcb444bce58b945de8574"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaff68c0ba3e9e25dfe5e39153301862f8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">XAxiDma_Busy</a> (<a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *InstancePtr, int Direction)</td></tr>
<tr class="memdesc:gaff68c0ba3e9e25dfe5e39153301862f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function checks whether specified DMA channel is busy.  <a href="#gaff68c0ba3e9e25dfe5e39153301862f8">More...</a><br /></td></tr>
<tr class="separator:gaff68c0ba3e9e25dfe5e39153301862f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5becc8b0f9945af34e372ced2b37aebb"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">XAxiDma_SelectKeyHole</a> (<a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *InstancePtr, int Direction, int Select)</td></tr>
<tr class="memdesc:ga5becc8b0f9945af34e372ced2b37aebb"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function Enable or Disable KeyHole Feature.  <a href="#ga5becc8b0f9945af34e372ced2b37aebb">More...</a><br /></td></tr>
<tr class="separator:ga5becc8b0f9945af34e372ced2b37aebb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d93bfcf1c3e34cb9fc4a22da6148dc5"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">XAxiDma_SelectCyclicMode</a> (<a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *InstancePtr, int Direction, int Select)</td></tr>
<tr class="memdesc:ga2d93bfcf1c3e34cb9fc4a22da6148dc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function Enable or Disable Cyclic Mode Feature.  <a href="#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">More...</a><br /></td></tr>
<tr class="separator:ga2d93bfcf1c3e34cb9fc4a22da6148dc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga32ca6099d7926297a4c17cdb4a19511b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer</a> (<a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *InstancePtr, UINTPTR BuffAddr, u32 Length, int Direction)</td></tr>
<tr class="memdesc:ga32ca6099d7926297a4c17cdb4a19511b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function does one simple transfer submission.  <a href="#ga32ca6099d7926297a4c17cdb4a19511b">More...</a><br /></td></tr>
<tr class="separator:ga32ca6099d7926297a4c17cdb4a19511b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0cbcf5259635ea3c336fe5413c98f75c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_axi_dma___config.html">XAxiDma_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga0cbcf5259635ea3c336fe5413c98f75c">XAxiDma_LookupConfig</a> (u32 DeviceId)</td></tr>
<tr class="memdesc:ga0cbcf5259635ea3c336fe5413c98f75c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Look up the hardware configuration for a device instance.  <a href="#ga0cbcf5259635ea3c336fe5413c98f75c">More...</a><br /></td></tr>
<tr class="separator:ga0cbcf5259635ea3c336fe5413c98f75c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4ea3039216916336ae1c7598ff26afc"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gad4ea3039216916336ae1c7598ff26afc">XAxiDma_Selftest</a> (<a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *InstancePtr)</td></tr>
<tr class="memdesc:gad4ea3039216916336ae1c7598ff26afc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Runs a self-test on the driver/device.  <a href="#gad4ea3039216916336ae1c7598ff26afc">More...</a><br /></td></tr>
<tr class="separator:gad4ea3039216916336ae1c7598ff26afc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4056035d8e7c90a68fa954c60d021e07"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07">XAxiDma_BdSetLength</a> (<a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdPtr, u32 LenBytes, u32 LengthMask)</td></tr>
<tr class="memdesc:ga4056035d8e7c90a68fa954c60d021e07"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the length field for the given BD.  <a href="#ga4056035d8e7c90a68fa954c60d021e07">More...</a><br /></td></tr>
<tr class="separator:ga4056035d8e7c90a68fa954c60d021e07"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac1a9cb01ba6cd686ee08245f5e08cb22"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr</a> (<a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdPtr, UINTPTR Addr)</td></tr>
<tr class="memdesc:gac1a9cb01ba6cd686ee08245f5e08cb22"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the BD's buffer address.  <a href="#gac1a9cb01ba6cd686ee08245f5e08cb22">More...</a><br /></td></tr>
<tr class="separator:gac1a9cb01ba6cd686ee08245f5e08cb22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8947514b5acfea6298d0f969f3d2b97e"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">XAxiDma_BdSetBufAddrMicroMode</a> (<a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdPtr, UINTPTR Addr)</td></tr>
<tr class="memdesc:ga8947514b5acfea6298d0f969f3d2b97e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the BD's buffer address when configured for Micro Mode.  <a href="#ga8947514b5acfea6298d0f969f3d2b97e">More...</a><br /></td></tr>
<tr class="separator:ga8947514b5acfea6298d0f969f3d2b97e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafc6434a23594c20c2b601f010a979e48"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gafc6434a23594c20c2b601f010a979e48">XAxiDma_BdSetAppWord</a> (<a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdPtr, int Offset, u32 Word)</td></tr>
<tr class="memdesc:gafc6434a23594c20c2b601f010a979e48"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the APP word at the specified APP word offset for a BD.  <a href="#gafc6434a23594c20c2b601f010a979e48">More...</a><br /></td></tr>
<tr class="separator:gafc6434a23594c20c2b601f010a979e48"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d2814e4249884e68fe9e6f370920ca4"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga9d2814e4249884e68fe9e6f370920ca4">XAxiDma_BdGetAppWord</a> (<a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdPtr, int Offset, int *Valid)</td></tr>
<tr class="memdesc:ga9d2814e4249884e68fe9e6f370920ca4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the APP word at the specified APP word offset for a BD.  <a href="#ga9d2814e4249884e68fe9e6f370920ca4">More...</a><br /></td></tr>
<tr class="separator:ga9d2814e4249884e68fe9e6f370920ca4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4eb2615ac89054e982c3f3c37f0ddb52"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">XAxiDma_BdSetCtrl</a> (<a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdPtr, u32 Data)</td></tr>
<tr class="memdesc:ga4eb2615ac89054e982c3f3c37f0ddb52"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the control bits for a BD.  <a href="#ga4eb2615ac89054e982c3f3c37f0ddb52">More...</a><br /></td></tr>
<tr class="separator:ga4eb2615ac89054e982c3f3c37f0ddb52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga53983f629aba5b4ebf27f803a7a9284e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">XAxiDma_DumpBd</a> (<a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdPtr)</td></tr>
<tr class="memdesc:ga53983f629aba5b4ebf27f803a7a9284e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Dump the fields of a BD.  <a href="#ga53983f629aba5b4ebf27f803a7a9284e">More...</a><br /></td></tr>
<tr class="separator:ga53983f629aba5b4ebf27f803a7a9284e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39ee7d89e4453276d615849acad27fde"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr)</td></tr>
<tr class="memdesc:ga39ee7d89e4453276d615849acad27fde"><td class="mdescLeft">&#160;</td><td class="mdescRight">Update Current Descriptor.  <a href="#ga39ee7d89e4453276d615849acad27fde">More...</a><br /></td></tr>
<tr class="separator:ga39ee7d89e4453276d615849acad27fde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c6d6f492642dd355478c3a853556d6b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, UINTPTR PhysAddr, UINTPTR VirtAddr, u32 Alignment, int BdCount)</td></tr>
<tr class="memdesc:ga5c6d6f492642dd355478c3a853556d6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring.  <a href="#ga5c6d6f492642dd355478c3a853556d6b">More...</a><br /></td></tr>
<tr class="separator:ga5c6d6f492642dd355478c3a853556d6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad044df5bd676a71226411ba7f78ef20b"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, <a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *SrcBdPtr)</td></tr>
<tr class="memdesc:gad044df5bd676a71226411ba7f78ef20b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clone the given BD into every BD in the ring.  <a href="#gad044df5bd676a71226411ba7f78ef20b">More...</a><br /></td></tr>
<tr class="separator:gad044df5bd676a71226411ba7f78ef20b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b38bc9220c391823219937580bd816f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr)</td></tr>
<tr class="memdesc:ga7b38bc9220c391823219937580bd816f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed.  <a href="#ga7b38bc9220c391823219937580bd816f">More...</a><br /></td></tr>
<tr class="separator:ga7b38bc9220c391823219937580bd816f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaafd18a1df185c30b4745c147e3295ac3"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3">XAxiDma_BdRingStart</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr)</td></tr>
<tr class="memdesc:gaafd18a1df185c30b4745c147e3295ac3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed.  <a href="#gaafd18a1df185c30b4745c147e3295ac3">More...</a><br /></td></tr>
<tr class="separator:gaafd18a1df185c30b4745c147e3295ac3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaebba5c661e04485582e887e74dbeb94"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">XAxiDma_BdRingSetCoalesce</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, u32 Counter, u32 Timer)</td></tr>
<tr class="memdesc:gaaebba5c661e04485582e887e74dbeb94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set interrupt coalescing parameters for the given descriptor ring channel.  <a href="#gaaebba5c661e04485582e887e74dbeb94">More...</a><br /></td></tr>
<tr class="separator:gaaebba5c661e04485582e887e74dbeb94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d3794bbccf028da8e94407d061dfc68"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">XAxiDma_BdRingGetCoalesce</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, u32 *CounterPtr, u32 *TimerPtr)</td></tr>
<tr class="memdesc:ga0d3794bbccf028da8e94407d061dfc68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve current interrupt coalescing parameters from the given descriptor ring channel.  <a href="#ga0d3794bbccf028da8e94407d061dfc68">More...</a><br /></td></tr>
<tr class="separator:ga0d3794bbccf028da8e94407d061dfc68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga44003cd704b7d4868d1dc00bb433a91f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f">XAxiDma_BdRingAlloc</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, int NumBd, <a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> **BdSetPtr)</td></tr>
<tr class="memdesc:ga44003cd704b7d4868d1dc00bb433a91f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserve locations in the BD ring.  <a href="#ga44003cd704b7d4868d1dc00bb433a91f">More...</a><br /></td></tr>
<tr class="separator:ga44003cd704b7d4868d1dc00bb433a91f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac58b1ab7a89890142baf67211772d3ce"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce">XAxiDma_BdRingUnAlloc</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, int NumBd, <a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdSetPtr)</td></tr>
<tr class="memdesc:gac58b1ab7a89890142baf67211772d3ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fully or partially undo an <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a> operation.  <a href="#gac58b1ab7a89890142baf67211772d3ce">More...</a><br /></td></tr>
<tr class="separator:gac58b1ab7a89890142baf67211772d3ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaac81111b373e373be7dd3989fffffe7b"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, int NumBd, <a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdSetPtr)</td></tr>
<tr class="memdesc:gaac81111b373e373be7dd3989fffffe7b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enqueue a set of BDs to hardware that were previously allocated by <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a>.  <a href="#gaac81111b373e373be7dd3989fffffe7b">More...</a><br /></td></tr>
<tr class="separator:gaac81111b373e373be7dd3989fffffe7b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e5d328b4d4a247d1530fac3efe4c59c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, int BdLimit, <a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> **BdSetPtr)</td></tr>
<tr class="memdesc:ga1e5d328b4d4a247d1530fac3efe4c59c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns a set of BD(s) that have been processed by hardware.  <a href="#ga1e5d328b4d4a247d1530fac3efe4c59c">More...</a><br /></td></tr>
<tr class="separator:ga1e5d328b4d4a247d1530fac3efe4c59c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2ac76e5a39486896cd484e51d2898c7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7">XAxiDma_BdRingFree</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, int NumBd, <a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdSetPtr)</td></tr>
<tr class="memdesc:gad2ac76e5a39486896cd484e51d2898c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frees a set of BDs that had been previously retrieved with <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>.  <a href="#gad2ac76e5a39486896cd484e51d2898c7">More...</a><br /></td></tr>
<tr class="separator:gad2ac76e5a39486896cd484e51d2898c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64cf3c732bc803da742c256ab6372e0e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr)</td></tr>
<tr class="memdesc:ga64cf3c732bc803da742c256ab6372e0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check the internal data structures of the BD ring for the provided channel.  <a href="#ga64cf3c732bc803da742c256ab6372e0e">More...</a><br /></td></tr>
<tr class="separator:ga64cf3c732bc803da742c256ab6372e0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaffa661a9a2467c1e274842c147531cea"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr)</td></tr>
<tr class="memdesc:gaffa661a9a2467c1e274842c147531cea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Dump the registers for a channel.  <a href="#gaffa661a9a2467c1e274842c147531cea">More...</a><br /></td></tr>
<tr class="separator:gaffa661a9a2467c1e274842c147531cea"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
DMA Transfer Direction</h2></td></tr>
<tr class="memitem:ga6d21b8539047064dabb29f2019631d7a"><td class="memItemLeft" align="right" valign="top"><a id="ga6d21b8539047064dabb29f2019631d7a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_DMA_TO_DEVICE</b>&#160;&#160;&#160;0x00</td></tr>
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<tr class="memitem:ga8d084cfadd0109365865418e7cde7729"><td class="memItemLeft" align="right" valign="top"><a id="ga8d084cfadd0109365865418e7cde7729"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_DEVICE_TO_DMA</b>&#160;&#160;&#160;0x01</td></tr>
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</table><table class="memberdecls">
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Buffer Descriptor Alignment</h2></td></tr>
<tr class="memitem:ga7957d90570574e9c7a7ee308b290ecab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga7957d90570574e9c7a7ee308b290ecab">XAXIDMA_BD_MINIMUM_ALIGNMENT</a>&#160;&#160;&#160;0x40</td></tr>
<tr class="memdesc:ga7957d90570574e9c7a7ee308b290ecab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Minimum byte alignment requirement for descriptors to satisfy both hardware/software needs.  <a href="#ga7957d90570574e9c7a7ee308b290ecab">More...</a><br /></td></tr>
<tr class="separator:ga7957d90570574e9c7a7ee308b290ecab"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
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Micro DMA Buffer Address Alignment</h2></td></tr>
<tr class="memitem:gaf0f7e862f42d26800868816eea2a949b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaf0f7e862f42d26800868816eea2a949b">XAXIDMA_MICROMODE_MIN_BUF_ALIGN</a>&#160;&#160;&#160;0xFFF</td></tr>
<tr class="memdesc:gaf0f7e862f42d26800868816eea2a949b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Minimum byte alignment requirement for buffer address in Micro DMA mode.  <a href="#gaf0f7e862f42d26800868816eea2a949b">More...</a><br /></td></tr>
<tr class="separator:gaf0f7e862f42d26800868816eea2a949b"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Maximum transfer length</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp9719975d4db7edfda8877c2b11b1ec78"></a>This is determined by hardware </p>
</td></tr>
<tr class="memitem:ga8d030b2413647190f71b14b635a9ea2b"><td class="memItemLeft" align="right" valign="top"><a id="ga8d030b2413647190f71b14b635a9ea2b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_MAX_TRANSFER_LEN</b>&#160;&#160;&#160;0x7FFFFF  /* Max length hw supports */</td></tr>
<tr class="separator:ga8d030b2413647190f71b14b635a9ea2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga58140e7d518a5cec1c601b60c5b9adec"><td class="memItemLeft" align="right" valign="top"><a id="ga58140e7d518a5cec1c601b60c5b9adec"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_MCHAN_MAX_TRANSFER_LEN</b></td></tr>
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Device registers</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe905567f3f1e4630e21d2f8192509576"></a>Register sets on TX and RX channels are identical </p>
</td></tr>
<tr class="memitem:ga88232281611059fd669f0339888cd44e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga88232281611059fd669f0339888cd44e">XAXIDMA_TX_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:ga88232281611059fd669f0339888cd44e"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX channel registers base offset.  <a href="#ga88232281611059fd669f0339888cd44e">More...</a><br /></td></tr>
<tr class="separator:ga88232281611059fd669f0339888cd44e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadfdc083e0b249c04624a66e700d7a7c4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a>&#160;&#160;&#160;0x00000030</td></tr>
<tr class="memdesc:gadfdc083e0b249c04624a66e700d7a7c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX channel registers base offset.  <a href="#gadfdc083e0b249c04624a66e700d7a7c4">More...</a><br /></td></tr>
<tr class="separator:gadfdc083e0b249c04624a66e700d7a7c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8534b07ed878f92d2062dc1680fb0391"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:ga8534b07ed878f92d2062dc1680fb0391"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel control.  <a href="#ga8534b07ed878f92d2062dc1680fb0391">More...</a><br /></td></tr>
<tr class="separator:ga8534b07ed878f92d2062dc1680fb0391"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga50d6957f8447d4eab9e444666730f692"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga50d6957f8447d4eab9e444666730f692"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status.  <a href="#ga50d6957f8447d4eab9e444666730f692">More...</a><br /></td></tr>
<tr class="separator:ga50d6957f8447d4eab9e444666730f692"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga24b47801eed2ab0ba326b8b40d24f2b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">XAXIDMA_CDESC_OFFSET</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga24b47801eed2ab0ba326b8b40d24f2b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current descriptor pointer.  <a href="#ga24b47801eed2ab0ba326b8b40d24f2b1">More...</a><br /></td></tr>
<tr class="separator:ga24b47801eed2ab0ba326b8b40d24f2b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00ee7a235750d8795961223455407051"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga00ee7a235750d8795961223455407051">XAXIDMA_CDESC_MSB_OFFSET</a>&#160;&#160;&#160;0x0000000C</td></tr>
<tr class="memdesc:ga00ee7a235750d8795961223455407051"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current descriptor pointer.  <a href="#ga00ee7a235750d8795961223455407051">More...</a><br /></td></tr>
<tr class="separator:ga00ee7a235750d8795961223455407051"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8626fb2bed7230a2c82a7e1db0ddd35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac8626fb2bed7230a2c82a7e1db0ddd35">XAXIDMA_TDESC_OFFSET</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gac8626fb2bed7230a2c82a7e1db0ddd35"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tail descriptor pointer.  <a href="#gac8626fb2bed7230a2c82a7e1db0ddd35">More...</a><br /></td></tr>
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<tr class="memitem:ga6063ffb7cb46cdca589e6f31069f7758"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga6063ffb7cb46cdca589e6f31069f7758">XAXIDMA_TDESC_MSB_OFFSET</a>&#160;&#160;&#160;0x00000014</td></tr>
<tr class="memdesc:ga6063ffb7cb46cdca589e6f31069f7758"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tail descriptor pointer.  <a href="#ga6063ffb7cb46cdca589e6f31069f7758">More...</a><br /></td></tr>
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<tr class="memitem:ga386fad6446792679302b362ed34022cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga386fad6446792679302b362ed34022cf">XAXIDMA_SRCADDR_OFFSET</a>&#160;&#160;&#160;0x00000018</td></tr>
<tr class="memdesc:ga386fad6446792679302b362ed34022cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Simple mode source address pointer.  <a href="#ga386fad6446792679302b362ed34022cf">More...</a><br /></td></tr>
<tr class="separator:ga386fad6446792679302b362ed34022cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafaafc49751e690d818d604efe368c481"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gafaafc49751e690d818d604efe368c481">XAXIDMA_SRCADDR_MSB_OFFSET</a>&#160;&#160;&#160;0x0000001C</td></tr>
<tr class="memdesc:gafaafc49751e690d818d604efe368c481"><td class="mdescLeft">&#160;</td><td class="mdescRight">Simple mode source address pointer.  <a href="#gafaafc49751e690d818d604efe368c481">More...</a><br /></td></tr>
<tr class="separator:gafaafc49751e690d818d604efe368c481"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4e98e82ed389c23918315d833b457ea9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga4e98e82ed389c23918315d833b457ea9">XAXIDMA_DESTADDR_OFFSET</a>&#160;&#160;&#160;0x00000018</td></tr>
<tr class="memdesc:ga4e98e82ed389c23918315d833b457ea9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Simple mode destination address pointer.  <a href="#ga4e98e82ed389c23918315d833b457ea9">More...</a><br /></td></tr>
<tr class="separator:ga4e98e82ed389c23918315d833b457ea9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3a54e372851dbae81c33997ef2ba8d2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga3a54e372851dbae81c33997ef2ba8d2f">XAXIDMA_DESTADDR_MSB_OFFSET</a>&#160;&#160;&#160;0x0000001C</td></tr>
<tr class="memdesc:ga3a54e372851dbae81c33997ef2ba8d2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Simple mode destination address pointer.  <a href="#ga3a54e372851dbae81c33997ef2ba8d2f">More...</a><br /></td></tr>
<tr class="separator:ga3a54e372851dbae81c33997ef2ba8d2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7ede468ba17bf106101d4850184dc74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaa7ede468ba17bf106101d4850184dc74">XAXIDMA_BUFFLEN_OFFSET</a>&#160;&#160;&#160;0x00000028</td></tr>
<tr class="memdesc:gaa7ede468ba17bf106101d4850184dc74"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tail descriptor pointer.  <a href="#gaa7ede468ba17bf106101d4850184dc74">More...</a><br /></td></tr>
<tr class="separator:gaa7ede468ba17bf106101d4850184dc74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab26580f9b4a94b3ab1d373ddeab7b3b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gab26580f9b4a94b3ab1d373ddeab7b3b6">XAXIDMA_SGCTL_OFFSET</a>&#160;&#160;&#160;0x0000002c</td></tr>
<tr class="memdesc:gab26580f9b4a94b3ab1d373ddeab7b3b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">SG Control Register.  <a href="#gab26580f9b4a94b3ab1d373ddeab7b3b6">More...</a><br /></td></tr>
<tr class="separator:gab26580f9b4a94b3ab1d373ddeab7b3b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79d2eca90f2554b8c893b2f9a70c795c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">XAXIDMA_RX_CDESC0_OFFSET</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga79d2eca90f2554b8c893b2f9a70c795c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi-Channel DMA Descriptor Offsets.  <a href="#ga79d2eca90f2554b8c893b2f9a70c795c">More...</a><br /></td></tr>
<tr class="separator:ga79d2eca90f2554b8c893b2f9a70c795c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad80414a88feceb1da4b9f77096d1d590"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gad80414a88feceb1da4b9f77096d1d590">XAXIDMA_RX_CDESC0_MSB_OFFSET</a>&#160;&#160;&#160;0x00000044</td></tr>
<tr class="memdesc:gad80414a88feceb1da4b9f77096d1d590"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Current Descriptor 0.  <a href="#gad80414a88feceb1da4b9f77096d1d590">More...</a><br /></td></tr>
<tr class="separator:gad80414a88feceb1da4b9f77096d1d590"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadfa4d02f0dd1fd005c695e9977457722"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadfa4d02f0dd1fd005c695e9977457722">XAXIDMA_RX_TDESC0_OFFSET</a>&#160;&#160;&#160;0x00000048</td></tr>
<tr class="memdesc:gadfa4d02f0dd1fd005c695e9977457722"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Tail Descriptor 0.  <a href="#gadfa4d02f0dd1fd005c695e9977457722">More...</a><br /></td></tr>
<tr class="separator:gadfa4d02f0dd1fd005c695e9977457722"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa9b5991af857e7bac763311fd917978d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaa9b5991af857e7bac763311fd917978d">XAXIDMA_RX_TDESC0_MSB_OFFSET</a>&#160;&#160;&#160;0x0000004C</td></tr>
<tr class="memdesc:gaa9b5991af857e7bac763311fd917978d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Tail Descriptor 0.  <a href="#gaa9b5991af857e7bac763311fd917978d">More...</a><br /></td></tr>
<tr class="separator:gaa9b5991af857e7bac763311fd917978d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6fc559cbc93b62195de6ecaf25492467"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">XAXIDMA_RX_NDESC_OFFSET</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga6fc559cbc93b62195de6ecaf25492467"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Next Descriptor Offset.  <a href="#ga6fc559cbc93b62195de6ecaf25492467">More...</a><br /></td></tr>
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Bitmasks of XAXIDMA_CR_OFFSET register</h2></td></tr>
<tr class="memitem:gab0ebdf6b7776e79941efe1325aac5aa9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gab0ebdf6b7776e79941efe1325aac5aa9">XAXIDMA_CR_RUNSTOP_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gab0ebdf6b7776e79941efe1325aac5aa9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start/stop DMA channel.  <a href="#gab0ebdf6b7776e79941efe1325aac5aa9">More...</a><br /></td></tr>
<tr class="separator:gab0ebdf6b7776e79941efe1325aac5aa9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga33fda61f0837d37da36d3b72b90b0fba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga33fda61f0837d37da36d3b72b90b0fba">XAXIDMA_CR_RESET_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga33fda61f0837d37da36d3b72b90b0fba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset DMA engine.  <a href="#ga33fda61f0837d37da36d3b72b90b0fba">More...</a><br /></td></tr>
<tr class="separator:ga33fda61f0837d37da36d3b72b90b0fba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bdf83c8ba16d8217a2a6486a9b5b521"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga8bdf83c8ba16d8217a2a6486a9b5b521">XAXIDMA_CR_KEYHOLE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga8bdf83c8ba16d8217a2a6486a9b5b521"><td class="mdescLeft">&#160;</td><td class="mdescRight">Keyhole feature.  <a href="#ga8bdf83c8ba16d8217a2a6486a9b5b521">More...</a><br /></td></tr>
<tr class="separator:ga8bdf83c8ba16d8217a2a6486a9b5b521"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d34bf268de2f2ef4d32351043835f68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga2d34bf268de2f2ef4d32351043835f68">XAXIDMA_CR_CYCLIC_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga2d34bf268de2f2ef4d32351043835f68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cyclic Mode.  <a href="#ga2d34bf268de2f2ef4d32351043835f68">More...</a><br /></td></tr>
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Bitmasks of XAXIDMA_SR_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp51b9d9ccef41896c28e614a92054e294"></a>This register reports status of a DMA channel, including run/stop/idle state, errors, and interrupts (note that interrupt masks are shared with XAXIDMA_CR_OFFSET register, and are defined in the <em>IRQ</em> section.</p>
<p>The interrupt coalescing threshold value and delay counter value are also shared with XAXIDMA_CR_OFFSET register, and are defined in a later section. </p>
</td></tr>
<tr class="memitem:ga70671c3d8cd1e51c56723e298d268cce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga70671c3d8cd1e51c56723e298d268cce">XAXIDMA_HALTED_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga70671c3d8cd1e51c56723e298d268cce"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA channel halted.  <a href="#ga70671c3d8cd1e51c56723e298d268cce">More...</a><br /></td></tr>
<tr class="separator:ga70671c3d8cd1e51c56723e298d268cce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa3538e8c2a6e024641259c85368667f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaa3538e8c2a6e024641259c85368667f0">XAXIDMA_IDLE_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaa3538e8c2a6e024641259c85368667f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA channel idle.  <a href="#gaa3538e8c2a6e024641259c85368667f0">More...</a><br /></td></tr>
<tr class="separator:gaa3538e8c2a6e024641259c85368667f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga87ac559811703a8ca33fc6b427913f2b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga87ac559811703a8ca33fc6b427913f2b">XAXIDMA_ERR_INTERNAL_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga87ac559811703a8ca33fc6b427913f2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Datamover internal err.  <a href="#ga87ac559811703a8ca33fc6b427913f2b">More...</a><br /></td></tr>
<tr class="separator:ga87ac559811703a8ca33fc6b427913f2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d50743f6c9d6474561f6727eb956915"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga6d50743f6c9d6474561f6727eb956915">XAXIDMA_ERR_SLAVE_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga6d50743f6c9d6474561f6727eb956915"><td class="mdescLeft">&#160;</td><td class="mdescRight">Datamover slave err.  <a href="#ga6d50743f6c9d6474561f6727eb956915">More...</a><br /></td></tr>
<tr class="separator:ga6d50743f6c9d6474561f6727eb956915"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa19b93d226e97afd08d3869dc530b692"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaa19b93d226e97afd08d3869dc530b692">XAXIDMA_ERR_DECODE_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gaa19b93d226e97afd08d3869dc530b692"><td class="mdescLeft">&#160;</td><td class="mdescRight">Datamover decode err.  <a href="#gaa19b93d226e97afd08d3869dc530b692">More...</a><br /></td></tr>
<tr class="separator:gaa19b93d226e97afd08d3869dc530b692"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f9ef0d10a7456a25a4b244955659d65"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga1f9ef0d10a7456a25a4b244955659d65">XAXIDMA_ERR_SG_INT_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga1f9ef0d10a7456a25a4b244955659d65"><td class="mdescLeft">&#160;</td><td class="mdescRight">SG internal err.  <a href="#ga1f9ef0d10a7456a25a4b244955659d65">More...</a><br /></td></tr>
<tr class="separator:ga1f9ef0d10a7456a25a4b244955659d65"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0f0d25fd68716e868742115c9a28c18c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga0f0d25fd68716e868742115c9a28c18c">XAXIDMA_ERR_SG_SLV_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga0f0d25fd68716e868742115c9a28c18c"><td class="mdescLeft">&#160;</td><td class="mdescRight">SG slave err.  <a href="#ga0f0d25fd68716e868742115c9a28c18c">More...</a><br /></td></tr>
<tr class="separator:ga0f0d25fd68716e868742115c9a28c18c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga43ecb16ea8e8d09a33364a17610d8909"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga43ecb16ea8e8d09a33364a17610d8909">XAXIDMA_ERR_SG_DEC_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga43ecb16ea8e8d09a33364a17610d8909"><td class="mdescLeft">&#160;</td><td class="mdescRight">SG decode err.  <a href="#ga43ecb16ea8e8d09a33364a17610d8909">More...</a><br /></td></tr>
<tr class="separator:ga43ecb16ea8e8d09a33364a17610d8909"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4102192c408420feb5b7db14d47c6d5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga4102192c408420feb5b7db14d47c6d5c">XAXIDMA_ERR_ALL_MASK</a>&#160;&#160;&#160;0x00000770</td></tr>
<tr class="memdesc:ga4102192c408420feb5b7db14d47c6d5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">All errors.  <a href="#ga4102192c408420feb5b7db14d47c6d5c">More...</a><br /></td></tr>
<tr class="separator:ga4102192c408420feb5b7db14d47c6d5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmask for interrupts</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp02a1bad3c75458826a49ba879f761eee"></a>These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register </p>
</td></tr>
<tr class="memitem:gae420f2ad87e1e00456a6ee3a80d2480d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gae420f2ad87e1e00456a6ee3a80d2480d">XAXIDMA_IRQ_IOC_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:gae420f2ad87e1e00456a6ee3a80d2480d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Completion intr.  <a href="#gae420f2ad87e1e00456a6ee3a80d2480d">More...</a><br /></td></tr>
<tr class="separator:gae420f2ad87e1e00456a6ee3a80d2480d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc4a45d09bcbf852f29b880935d607dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadc4a45d09bcbf852f29b880935d607dc">XAXIDMA_IRQ_DELAY_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:gadc4a45d09bcbf852f29b880935d607dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay interrupt.  <a href="#gadc4a45d09bcbf852f29b880935d607dc">More...</a><br /></td></tr>
<tr class="separator:gadc4a45d09bcbf852f29b880935d607dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ceb68e74761910e4253795a9b4992cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga6ceb68e74761910e4253795a9b4992cf">XAXIDMA_IRQ_ERROR_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:ga6ceb68e74761910e4253795a9b4992cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error interrupt.  <a href="#ga6ceb68e74761910e4253795a9b4992cf">More...</a><br /></td></tr>
<tr class="separator:ga6ceb68e74761910e4253795a9b4992cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8347e41a5c01bdabefce9c8484a7ced1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>&#160;&#160;&#160;0x00007000</td></tr>
<tr class="memdesc:ga8347e41a5c01bdabefce9c8484a7ced1"><td class="mdescLeft">&#160;</td><td class="mdescRight">All interrupts.  <a href="#ga8347e41a5c01bdabefce9c8484a7ced1">More...</a><br /></td></tr>
<tr class="separator:ga8347e41a5c01bdabefce9c8484a7ced1"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Bitmask and shift for delay and coalesce</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp7d080d6a9fae95527adc10fd14697fe7"></a>These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register </p>
</td></tr>
<tr class="memitem:gae3ad7ae6b5814b99de67bba06ec77ed1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gae3ad7ae6b5814b99de67bba06ec77ed1">XAXIDMA_DELAY_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:gae3ad7ae6b5814b99de67bba06ec77ed1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay timeout counter.  <a href="#gae3ad7ae6b5814b99de67bba06ec77ed1">More...</a><br /></td></tr>
<tr class="separator:gae3ad7ae6b5814b99de67bba06ec77ed1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga280fd988ea7ec3fadfe7cf1293f39e36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga280fd988ea7ec3fadfe7cf1293f39e36">XAXIDMA_COALESCE_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:ga280fd988ea7ec3fadfe7cf1293f39e36"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coalesce counter.  <a href="#ga280fd988ea7ec3fadfe7cf1293f39e36">More...</a><br /></td></tr>
<tr class="separator:ga280fd988ea7ec3fadfe7cf1293f39e36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7152d174fbce44a674e0872a3d82c320"><td class="memItemLeft" align="right" valign="top"><a id="ga7152d174fbce44a674e0872a3d82c320"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_DELAY_SHIFT</b>&#160;&#160;&#160;24</td></tr>
<tr class="separator:ga7152d174fbce44a674e0872a3d82c320"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1628424aed5e5be66b41756c4f5eab04"><td class="memItemLeft" align="right" valign="top"><a id="ga1628424aed5e5be66b41756c4f5eab04"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_COALESCE_SHIFT</b>&#160;&#160;&#160;16</td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Buffer Descriptor offsets</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp4284acb9eab1123bbaf97dcfe7ce5a75"></a>USR* fields are defined by higher level IP.</p>
<p>setup for EMAC type devices. The first 13 words are used by hardware. All words after the 13rd word are for software use only. </p>
</td></tr>
<tr class="memitem:ga64e86b7df328bc7209a28152f86fd609"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga64e86b7df328bc7209a28152f86fd609">XAXIDMA_BD_NDESC_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:ga64e86b7df328bc7209a28152f86fd609"><td class="mdescLeft">&#160;</td><td class="mdescRight">Next descriptor pointer.  <a href="#ga64e86b7df328bc7209a28152f86fd609">More...</a><br /></td></tr>
<tr class="separator:ga64e86b7df328bc7209a28152f86fd609"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga730aa200407e3c7e38e6fad914ad1eb0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga730aa200407e3c7e38e6fad914ad1eb0">XAXIDMA_BD_NDESC_MSB_OFFSET</a>&#160;&#160;&#160;0x04</td></tr>
<tr class="memdesc:ga730aa200407e3c7e38e6fad914ad1eb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Next descriptor pointer.  <a href="#ga730aa200407e3c7e38e6fad914ad1eb0">More...</a><br /></td></tr>
<tr class="separator:ga730aa200407e3c7e38e6fad914ad1eb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bb69f2401305faa1d89fb8dc31e770f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">XAXIDMA_BD_BUFA_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:ga8bb69f2401305faa1d89fb8dc31e770f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer address.  <a href="#ga8bb69f2401305faa1d89fb8dc31e770f">More...</a><br /></td></tr>
<tr class="separator:ga8bb69f2401305faa1d89fb8dc31e770f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaccd48ccba559728721eac77a4acc23d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaccd48ccba559728721eac77a4acc23d1">XAXIDMA_BD_BUFA_MSB_OFFSET</a>&#160;&#160;&#160;0x0C</td></tr>
<tr class="memdesc:gaccd48ccba559728721eac77a4acc23d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer address.  <a href="#gaccd48ccba559728721eac77a4acc23d1">More...</a><br /></td></tr>
<tr class="separator:gaccd48ccba559728721eac77a4acc23d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6daf74c6d99207a0d8ba91a049e661c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:ga6daf74c6d99207a0d8ba91a049e661c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multichannel Control Fields.  <a href="#ga6daf74c6d99207a0d8ba91a049e661c6">More...</a><br /></td></tr>
<tr class="separator:ga6daf74c6d99207a0d8ba91a049e661c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga83d7d4d6e88ab44910242b61fcd7f8fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:ga83d7d4d6e88ab44910242b61fcd7f8fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">2D Transfer Sizes  <a href="#ga83d7d4d6e88ab44910242b61fcd7f8fe">More...</a><br /></td></tr>
<tr class="separator:ga83d7d4d6e88ab44910242b61fcd7f8fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac3372d0a1625537d5b637f40ca20f52c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>&#160;&#160;&#160;0x18</td></tr>
<tr class="memdesc:gac3372d0a1625537d5b637f40ca20f52c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control/buffer length.  <a href="#gac3372d0a1625537d5b637f40ca20f52c">More...</a><br /></td></tr>
<tr class="separator:gac3372d0a1625537d5b637f40ca20f52c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac71ad6cd79fc11e699bc10e3736fa08c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>&#160;&#160;&#160;0x1C</td></tr>
<tr class="memdesc:gac71ad6cd79fc11e699bc10e3736fa08c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status.  <a href="#gac71ad6cd79fc11e699bc10e3736fa08c">More...</a><br /></td></tr>
<tr class="separator:gac71ad6cd79fc11e699bc10e3736fa08c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace0f0376ed9e0aad3d3e3c80254b20b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gace0f0376ed9e0aad3d3e3c80254b20b4">XAXIDMA_BD_USR0_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:gace0f0376ed9e0aad3d3e3c80254b20b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">User IP specific word0.  <a href="#gace0f0376ed9e0aad3d3e3c80254b20b4">More...</a><br /></td></tr>
<tr class="separator:gace0f0376ed9e0aad3d3e3c80254b20b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d9d62be0e0ed11b18f185b62dc72f67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga7d9d62be0e0ed11b18f185b62dc72f67">XAXIDMA_BD_USR1_OFFSET</a>&#160;&#160;&#160;0x24</td></tr>
<tr class="memdesc:ga7d9d62be0e0ed11b18f185b62dc72f67"><td class="mdescLeft">&#160;</td><td class="mdescRight">User IP specific word1.  <a href="#ga7d9d62be0e0ed11b18f185b62dc72f67">More...</a><br /></td></tr>
<tr class="separator:ga7d9d62be0e0ed11b18f185b62dc72f67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc83ff22099fdf61a5237965ce082504"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadc83ff22099fdf61a5237965ce082504">XAXIDMA_BD_USR2_OFFSET</a>&#160;&#160;&#160;0x28</td></tr>
<tr class="memdesc:gadc83ff22099fdf61a5237965ce082504"><td class="mdescLeft">&#160;</td><td class="mdescRight">User IP specific word2.  <a href="#gadc83ff22099fdf61a5237965ce082504">More...</a><br /></td></tr>
<tr class="separator:gadc83ff22099fdf61a5237965ce082504"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1c5981447fe5ac113a6da3c1e19d6ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gae1c5981447fe5ac113a6da3c1e19d6ed">XAXIDMA_BD_USR3_OFFSET</a>&#160;&#160;&#160;0x2C</td></tr>
<tr class="memdesc:gae1c5981447fe5ac113a6da3c1e19d6ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">User IP specific word3.  <a href="#gae1c5981447fe5ac113a6da3c1e19d6ed">More...</a><br /></td></tr>
<tr class="separator:gae1c5981447fe5ac113a6da3c1e19d6ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ccae584923d0b6d0851a8bbae4528c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga1ccae584923d0b6d0851a8bbae4528c9">XAXIDMA_BD_USR4_OFFSET</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:ga1ccae584923d0b6d0851a8bbae4528c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">User IP specific word4.  <a href="#ga1ccae584923d0b6d0851a8bbae4528c9">More...</a><br /></td></tr>
<tr class="separator:ga1ccae584923d0b6d0851a8bbae4528c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga117e266cba3edbd1fd2f1e29305dcfc8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">XAXIDMA_BD_ID_OFFSET</a>&#160;&#160;&#160;0x34</td></tr>
<tr class="memdesc:ga117e266cba3edbd1fd2f1e29305dcfc8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sw ID.  <a href="#ga117e266cba3edbd1fd2f1e29305dcfc8">More...</a><br /></td></tr>
<tr class="separator:ga117e266cba3edbd1fd2f1e29305dcfc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga819b1b14cd4d386e588679105a8738a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">XAXIDMA_BD_HAS_STSCNTRL_OFFSET</a>&#160;&#160;&#160;0x38</td></tr>
<tr class="memdesc:ga819b1b14cd4d386e588679105a8738a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether has stscntrl strm.  <a href="#ga819b1b14cd4d386e588679105a8738a6">More...</a><br /></td></tr>
<tr class="separator:ga819b1b14cd4d386e588679105a8738a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga932a4ab54f38046e6635b9b87a584c79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga932a4ab54f38046e6635b9b87a584c79">XAXIDMA_BD_HAS_DRE_OFFSET</a>&#160;&#160;&#160;0x3C</td></tr>
<tr class="memdesc:ga932a4ab54f38046e6635b9b87a584c79"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether has DRE.  <a href="#ga932a4ab54f38046e6635b9b87a584c79">More...</a><br /></td></tr>
<tr class="separator:ga932a4ab54f38046e6635b9b87a584c79"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad40d36cf3371ad3d176835933dc85e4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gad40d36cf3371ad3d176835933dc85e4b">XAXIDMA_BD_HAS_DRE_MASK</a>&#160;&#160;&#160;0xF00</td></tr>
<tr class="memdesc:gad40d36cf3371ad3d176835933dc85e4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether has DRE mask.  <a href="#gad40d36cf3371ad3d176835933dc85e4b">More...</a><br /></td></tr>
<tr class="separator:gad40d36cf3371ad3d176835933dc85e4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafcbd1a131c650a5d6ceee6be15008a77"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gafcbd1a131c650a5d6ceee6be15008a77">XAXIDMA_BD_WORDLEN_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:gafcbd1a131c650a5d6ceee6be15008a77"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether has DRE mask.  <a href="#gafcbd1a131c650a5d6ceee6be15008a77">More...</a><br /></td></tr>
<tr class="separator:gafcbd1a131c650a5d6ceee6be15008a77"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac15dd4e956aa14d53a6f92544db468d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac15dd4e956aa14d53a6f92544db468d1">XAXIDMA_BD_HAS_DRE_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gac15dd4e956aa14d53a6f92544db468d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether has DRE shift.  <a href="#gac15dd4e956aa14d53a6f92544db468d1">More...</a><br /></td></tr>
<tr class="separator:gac15dd4e956aa14d53a6f92544db468d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3db5b1d09deab9660ff65c06136acbc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga3db5b1d09deab9660ff65c06136acbc5">XAXIDMA_BD_WORDLEN_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga3db5b1d09deab9660ff65c06136acbc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether has DRE shift.  <a href="#ga3db5b1d09deab9660ff65c06136acbc5">More...</a><br /></td></tr>
<tr class="separator:ga3db5b1d09deab9660ff65c06136acbc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9eac2b100bcdf0aa763d1575f43c822b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga9eac2b100bcdf0aa763d1575f43c822b">XAXIDMA_BD_START_CLEAR</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga9eac2b100bcdf0aa763d1575f43c822b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset to start clear.  <a href="#ga9eac2b100bcdf0aa763d1575f43c822b">More...</a><br /></td></tr>
<tr class="separator:ga9eac2b100bcdf0aa763d1575f43c822b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97ec6974f990aef9ea2298c1df5d72c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga97ec6974f990aef9ea2298c1df5d72c3">XAXIDMA_BD_BYTES_TO_CLEAR</a>&#160;&#160;&#160;48</td></tr>
<tr class="memdesc:ga97ec6974f990aef9ea2298c1df5d72c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">BD specific bytes to be cleared.  <a href="#ga97ec6974f990aef9ea2298c1df5d72c3">More...</a><br /></td></tr>
<tr class="separator:ga97ec6974f990aef9ea2298c1df5d72c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga751f6662ab9baed908685eef30d322b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga751f6662ab9baed908685eef30d322b8">XAXIDMA_BD_NUM_WORDS</a>&#160;&#160;&#160;16U</td></tr>
<tr class="memdesc:ga751f6662ab9baed908685eef30d322b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Total number of words for one BD.  <a href="#ga751f6662ab9baed908685eef30d322b8">More...</a><br /></td></tr>
<tr class="separator:ga751f6662ab9baed908685eef30d322b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8ddf1d33d85b0a7508b9a072d95bf14"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gae8ddf1d33d85b0a7508b9a072d95bf14">XAXIDMA_BD_HW_NUM_BYTES</a>&#160;&#160;&#160;52</td></tr>
<tr class="memdesc:gae8ddf1d33d85b0a7508b9a072d95bf14"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of bytes hw used.  <a href="#gae8ddf1d33d85b0a7508b9a072d95bf14">More...</a><br /></td></tr>
<tr class="separator:gae8ddf1d33d85b0a7508b9a072d95bf14"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60de0663a52d2daeee3aaad1f663716c"><td class="memItemLeft" align="right" valign="top"><a id="ga60de0663a52d2daeee3aaad1f663716c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_LAST_APPWORD</b>&#160;&#160;&#160;4</td></tr>
<tr class="separator:ga60de0663a52d2daeee3aaad1f663716c"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmasks of XAXIDMA_BD_CTRL_OFFSET register</h2></td></tr>
<tr class="memitem:gac279d381208f7f123ac07736702f8ff1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac279d381208f7f123ac07736702f8ff1">XAXIDMA_BD_CTRL_TXSOF_MASK</a>&#160;&#160;&#160;0x08000000</td></tr>
<tr class="memdesc:gac279d381208f7f123ac07736702f8ff1"><td class="mdescLeft">&#160;</td><td class="mdescRight">First tx packet.  <a href="#gac279d381208f7f123ac07736702f8ff1">More...</a><br /></td></tr>
<tr class="separator:gac279d381208f7f123ac07736702f8ff1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae9f4d328b9fb0bbdcadd6dc4c09fd4fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gae9f4d328b9fb0bbdcadd6dc4c09fd4fa">XAXIDMA_BD_CTRL_TXEOF_MASK</a>&#160;&#160;&#160;0x04000000</td></tr>
<tr class="memdesc:gae9f4d328b9fb0bbdcadd6dc4c09fd4fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last tx packet.  <a href="#gae9f4d328b9fb0bbdcadd6dc4c09fd4fa">More...</a><br /></td></tr>
<tr class="separator:gae9f4d328b9fb0bbdcadd6dc4c09fd4fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa409dba5ec46ad5a31953e22c4d3333f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gaa409dba5ec46ad5a31953e22c4d3333f">XAXIDMA_BD_CTRL_ALL_MASK</a>&#160;&#160;&#160;0x0C000000</td></tr>
<tr class="memdesc:gaa409dba5ec46ad5a31953e22c4d3333f"><td class="mdescLeft">&#160;</td><td class="mdescRight">All control bits.  <a href="#gaa409dba5ec46ad5a31953e22c4d3333f">More...</a><br /></td></tr>
<tr class="separator:gaa409dba5ec46ad5a31953e22c4d3333f"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmasks of XAXIDMA_BD_STS_OFFSET register</h2></td></tr>
<tr class="memitem:gadb7c73caf5e5007dcb56ea029d7390ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">XAXIDMA_BD_STS_COMPLETE_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:gadb7c73caf5e5007dcb56ea029d7390ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Completed.  <a href="#gadb7c73caf5e5007dcb56ea029d7390ba">More...</a><br /></td></tr>
<tr class="separator:gadb7c73caf5e5007dcb56ea029d7390ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae79c77f87a9887510ea53480c1e9a998"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gae79c77f87a9887510ea53480c1e9a998">XAXIDMA_BD_STS_DEC_ERR_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:gae79c77f87a9887510ea53480c1e9a998"><td class="mdescLeft">&#160;</td><td class="mdescRight">Decode error.  <a href="#gae79c77f87a9887510ea53480c1e9a998">More...</a><br /></td></tr>
<tr class="separator:gae79c77f87a9887510ea53480c1e9a998"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f7727fc139a6b3100a5a17cb110efa6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga1f7727fc139a6b3100a5a17cb110efa6">XAXIDMA_BD_STS_SLV_ERR_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:ga1f7727fc139a6b3100a5a17cb110efa6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave error.  <a href="#ga1f7727fc139a6b3100a5a17cb110efa6">More...</a><br /></td></tr>
<tr class="separator:ga1f7727fc139a6b3100a5a17cb110efa6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga09e502148e375f2d695d6d5d6e1797d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga09e502148e375f2d695d6d5d6e1797d2">XAXIDMA_BD_STS_INT_ERR_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:ga09e502148e375f2d695d6d5d6e1797d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Internal err.  <a href="#ga09e502148e375f2d695d6d5d6e1797d2">More...</a><br /></td></tr>
<tr class="separator:ga09e502148e375f2d695d6d5d6e1797d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8018932d7e9b743c4c5c76ab3d373de1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga8018932d7e9b743c4c5c76ab3d373de1">XAXIDMA_BD_STS_ALL_ERR_MASK</a>&#160;&#160;&#160;0x70000000</td></tr>
<tr class="memdesc:ga8018932d7e9b743c4c5c76ab3d373de1"><td class="mdescLeft">&#160;</td><td class="mdescRight">All errors.  <a href="#ga8018932d7e9b743c4c5c76ab3d373de1">More...</a><br /></td></tr>
<tr class="separator:ga8018932d7e9b743c4c5c76ab3d373de1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29915484fd9f840a8ab727cf83bbfe81"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga29915484fd9f840a8ab727cf83bbfe81">XAXIDMA_BD_STS_RXSOF_MASK</a>&#160;&#160;&#160;0x08000000</td></tr>
<tr class="memdesc:ga29915484fd9f840a8ab727cf83bbfe81"><td class="mdescLeft">&#160;</td><td class="mdescRight">First rx pkt.  <a href="#ga29915484fd9f840a8ab727cf83bbfe81">More...</a><br /></td></tr>
<tr class="separator:ga29915484fd9f840a8ab727cf83bbfe81"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga91b0504c621f6c06b0df4752fe65ee3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga91b0504c621f6c06b0df4752fe65ee3a">XAXIDMA_BD_STS_RXEOF_MASK</a>&#160;&#160;&#160;0x04000000</td></tr>
<tr class="memdesc:ga91b0504c621f6c06b0df4752fe65ee3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last rx pkt.  <a href="#ga91b0504c621f6c06b0df4752fe65ee3a">More...</a><br /></td></tr>
<tr class="separator:ga91b0504c621f6c06b0df4752fe65ee3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac433a776854849cbeaadcbed14132cb6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gac433a776854849cbeaadcbed14132cb6">XAXIDMA_BD_STS_ALL_MASK</a>&#160;&#160;&#160;0xFC000000</td></tr>
<tr class="memdesc:gac433a776854849cbeaadcbed14132cb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">All status bits.  <a href="#gac433a776854849cbeaadcbed14132cb6">More...</a><br /></td></tr>
<tr class="separator:gac433a776854849cbeaadcbed14132cb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmasks and shift values for XAXIDMA_BD_MCCTL_OFFSET register</h2></td></tr>
<tr class="memitem:ga4ea9159938fe936dea123b19fb183eb8"><td class="memItemLeft" align="right" valign="top"><a id="ga4ea9159938fe936dea123b19fb183eb8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_TDEST_FIELD_MASK</b>&#160;&#160;&#160;0x0000000F</td></tr>
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<tr class="memitem:ga8b971868c3a489967f9e0a464b1dd57c"><td class="memItemLeft" align="right" valign="top"><a id="ga8b971868c3a489967f9e0a464b1dd57c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_TID_FIELD_MASK</b>&#160;&#160;&#160;0x00000F00</td></tr>
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<tr class="memitem:gaf471f34da8477719021d6d4b6a556d9b"><td class="memItemLeft" align="right" valign="top"><a id="gaf471f34da8477719021d6d4b6a556d9b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_TUSER_FIELD_MASK</b>&#160;&#160;&#160;0x000F0000</td></tr>
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<tr class="memitem:ga07e72e534b1395058f8e520291dae3ff"><td class="memItemLeft" align="right" valign="top"><a id="ga07e72e534b1395058f8e520291dae3ff"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_ARCACHE_FIELD_MASK</b>&#160;&#160;&#160;0x0F000000</td></tr>
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<tr class="memitem:ga0e3414556458d79e8b9df51836633b16"><td class="memItemLeft" align="right" valign="top"><a id="ga0e3414556458d79e8b9df51836633b16"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_ARUSER_FIELD_MASK</b>&#160;&#160;&#160;0xF0000000</td></tr>
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<tr class="memitem:gaafc25bc10cd15e818a1d2f8b95f86cfb"><td class="memItemLeft" align="right" valign="top"><a id="gaafc25bc10cd15e818a1d2f8b95f86cfb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_TDEST_FIELD_SHIFT</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:gaafc25bc10cd15e818a1d2f8b95f86cfb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga78adf110257e059fe493d8f2dfa69b6a"><td class="memItemLeft" align="right" valign="top"><a id="ga78adf110257e059fe493d8f2dfa69b6a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_TID_FIELD_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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<tr class="memitem:ga88c7229708879df93f1505113d2658c1"><td class="memItemLeft" align="right" valign="top"><a id="ga88c7229708879df93f1505113d2658c1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_TUSER_FIELD_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:ga88c7229708879df93f1505113d2658c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c9c664e370859c1792146f98c76c34b"><td class="memItemLeft" align="right" valign="top"><a id="ga1c9c664e370859c1792146f98c76c34b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_ARCACHE_FIELD_SHIFT</b>&#160;&#160;&#160;24</td></tr>
<tr class="separator:ga1c9c664e370859c1792146f98c76c34b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaedace57317c6fe9a72a6dcbff50955ca"><td class="memItemLeft" align="right" valign="top"><a id="gaedace57317c6fe9a72a6dcbff50955ca"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_ARUSER_FIELD_SHIFT</b>&#160;&#160;&#160;28</td></tr>
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Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register</h2></td></tr>
<tr class="memitem:gabb6120d7369559e9ee19611387d5a123"><td class="memItemLeft" align="right" valign="top"><a id="gabb6120d7369559e9ee19611387d5a123"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_STRIDE_FIELD_MASK</b>&#160;&#160;&#160;0x0000FFFF</td></tr>
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<tr class="memitem:ga7c64f4da6fa4a20c9e277bfffda69e3d"><td class="memItemLeft" align="right" valign="top"><a id="ga7c64f4da6fa4a20c9e277bfffda69e3d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_VSIZE_FIELD_MASK</b>&#160;&#160;&#160;0xFFF80000</td></tr>
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<tr class="memitem:ga3206729ffb0431fd3b7f405d1146ec4a"><td class="memItemLeft" align="right" valign="top"><a id="ga3206729ffb0431fd3b7f405d1146ec4a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_STRIDE_FIELD_SHIFT</b>&#160;&#160;&#160;0</td></tr>
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<tr class="memitem:ga36e1ba2852b6f1311b1a68eb9e33a40d"><td class="memItemLeft" align="right" valign="top"><a id="ga36e1ba2852b6f1311b1a68eb9e33a40d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIDMA_BD_VSIZE_FIELD_SHIFT</b>&#160;&#160;&#160;19</td></tr>
<tr class="separator:ga36e1ba2852b6f1311b1a68eb9e33a40d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72fb349658447c76f6a58fdcc9ef8332"><td class="memItemLeft" align="right" valign="top"><a id="ga72fb349658447c76f6a58fdcc9ef8332"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAxiDma_In32</b>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="separator:ga72fb349658447c76f6a58fdcc9ef8332"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga67ce053696200c5a5273e5f62201c081"><td class="memItemLeft" align="right" valign="top"><a id="ga67ce053696200c5a5273e5f62201c081"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAxiDma_Out32</b>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="separator:ga67ce053696200c5a5273e5f62201c081"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadea426ef26fc5473a78723cd2b92aba5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XAxiDma_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:gadea426ef26fc5473a78723cd2b92aba5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the given register.  <a href="#gadea426ef26fc5473a78723cd2b92aba5">More...</a><br /></td></tr>
<tr class="separator:gadea426ef26fc5473a78723cd2b92aba5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga73dabf09bac8a209e0cc367f6ccdf44b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="memdesc:ga73dabf09bac8a209e0cc367f6ccdf44b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write the given register.  <a href="#ga73dabf09bac8a209e0cc367f6ccdf44b">More...</a><br /></td></tr>
<tr class="separator:ga73dabf09bac8a209e0cc367f6ccdf44b"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="gaccd48ccba559728721eac77a4acc23d1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaccd48ccba559728721eac77a4acc23d1">&#9670;&nbsp;</a></span>XAXIDMA_BD_BUFA_MSB_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_BUFA_MSB_OFFSET&#160;&#160;&#160;0x0C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Buffer address. </p>

</div>
</div>
<a id="ga8bb69f2401305faa1d89fb8dc31e770f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8bb69f2401305faa1d89fb8dc31e770f">&#9670;&nbsp;</a></span>XAXIDMA_BD_BUFA_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_BUFA_OFFSET&#160;&#160;&#160;0x08</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Buffer address. </p>

</div>
</div>
<a id="ga97ec6974f990aef9ea2298c1df5d72c3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga97ec6974f990aef9ea2298c1df5d72c3">&#9670;&nbsp;</a></span>XAXIDMA_BD_BYTES_TO_CLEAR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_BYTES_TO_CLEAR&#160;&#160;&#160;48</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>BD specific bytes to be cleared. </p>

</div>
</div>
<a id="gaa409dba5ec46ad5a31953e22c4d3333f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa409dba5ec46ad5a31953e22c4d3333f">&#9670;&nbsp;</a></span>XAXIDMA_BD_CTRL_ALL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_CTRL_ALL_MASK&#160;&#160;&#160;0x0C000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>All control bits. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">XAxiDma_BdSetCtrl()</a>.</p>

</div>
</div>
<a id="gac3372d0a1625537d5b637f40ca20f52c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac3372d0a1625537d5b637f40ca20f52c">&#9670;&nbsp;</a></span>XAXIDMA_BD_CTRL_LEN_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_CTRL_LEN_OFFSET&#160;&#160;&#160;0x18</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Control/buffer length. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">XAxiDma_BdSetCtrl()</a>, and <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07">XAxiDma_BdSetLength()</a>.</p>

</div>
</div>
<a id="gae9f4d328b9fb0bbdcadd6dc4c09fd4fa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae9f4d328b9fb0bbdcadd6dc4c09fd4fa">&#9670;&nbsp;</a></span>XAXIDMA_BD_CTRL_TXEOF_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_CTRL_TXEOF_MASK&#160;&#160;&#160;0x04000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Last tx packet. </p>

</div>
</div>
<a id="gac279d381208f7f123ac07736702f8ff1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac279d381208f7f123ac07736702f8ff1">&#9670;&nbsp;</a></span>XAXIDMA_BD_CTRL_TXSOF_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_CTRL_TXSOF_MASK&#160;&#160;&#160;0x08000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>First tx packet. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>

</div>
</div>
<a id="gad40d36cf3371ad3d176835933dc85e4b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad40d36cf3371ad3d176835933dc85e4b">&#9670;&nbsp;</a></span>XAXIDMA_BD_HAS_DRE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_HAS_DRE_MASK&#160;&#160;&#160;0xF00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Whether has DRE mask. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>.</p>

</div>
</div>
<a id="ga932a4ab54f38046e6635b9b87a584c79"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga932a4ab54f38046e6635b9b87a584c79">&#9670;&nbsp;</a></span>XAXIDMA_BD_HAS_DRE_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_HAS_DRE_OFFSET&#160;&#160;&#160;0x3C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Whether has DRE. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>.</p>

</div>
</div>
<a id="gac15dd4e956aa14d53a6f92544db468d1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac15dd4e956aa14d53a6f92544db468d1">&#9670;&nbsp;</a></span>XAXIDMA_BD_HAS_DRE_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_HAS_DRE_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Whether has DRE shift. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>

</div>
</div>
<a id="ga819b1b14cd4d386e588679105a8738a6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga819b1b14cd4d386e588679105a8738a6">&#9670;&nbsp;</a></span>XAXIDMA_BD_HAS_STSCNTRL_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET&#160;&#160;&#160;0x38</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Whether has stscntrl strm. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga9d2814e4249884e68fe9e6f370920ca4">XAxiDma_BdGetAppWord()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#gafc6434a23594c20c2b601f010a979e48">XAxiDma_BdSetAppWord()</a>.</p>

</div>
</div>
<a id="gae8ddf1d33d85b0a7508b9a072d95bf14"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae8ddf1d33d85b0a7508b9a072d95bf14">&#9670;&nbsp;</a></span>XAXIDMA_BD_HW_NUM_BYTES</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_HW_NUM_BYTES&#160;&#160;&#160;52</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Number of bytes hw used. </p>

</div>
</div>
<a id="ga117e266cba3edbd1fd2f1e29305dcfc8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga117e266cba3edbd1fd2f1e29305dcfc8">&#9670;&nbsp;</a></span>XAXIDMA_BD_ID_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_ID_OFFSET&#160;&#160;&#160;0x34</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Sw ID. </p>

</div>
</div>
<a id="ga6daf74c6d99207a0d8ba91a049e661c6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6daf74c6d99207a0d8ba91a049e661c6">&#9670;&nbsp;</a></span>XAXIDMA_BD_MCCTL_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_MCCTL_OFFSET&#160;&#160;&#160;0x10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Multichannel Control Fields. </p>

</div>
</div>
<a id="ga7957d90570574e9c7a7ee308b290ecab"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7957d90570574e9c7a7ee308b290ecab">&#9670;&nbsp;</a></span>XAXIDMA_BD_MINIMUM_ALIGNMENT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_MINIMUM_ALIGNMENT&#160;&#160;&#160;0x40</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Minimum byte alignment requirement for descriptors to satisfy both hardware/software needs. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>

</div>
</div>
<a id="ga730aa200407e3c7e38e6fad914ad1eb0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga730aa200407e3c7e38e6fad914ad1eb0">&#9670;&nbsp;</a></span>XAXIDMA_BD_NDESC_MSB_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_NDESC_MSB_OFFSET&#160;&#160;&#160;0x04</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Next descriptor pointer. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>

</div>
</div>
<a id="ga64e86b7df328bc7209a28152f86fd609"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga64e86b7df328bc7209a28152f86fd609">&#9670;&nbsp;</a></span>XAXIDMA_BD_NDESC_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_NDESC_OFFSET&#160;&#160;&#160;0x00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Next descriptor pointer. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>

</div>
</div>
<a id="ga751f6662ab9baed908685eef30d322b8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga751f6662ab9baed908685eef30d322b8">&#9670;&nbsp;</a></span>XAXIDMA_BD_NUM_WORDS</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_NUM_WORDS&#160;&#160;&#160;16U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Total number of words for one BD. </p>

</div>
</div>
<a id="ga9eac2b100bcdf0aa763d1575f43c822b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga9eac2b100bcdf0aa763d1575f43c822b">&#9670;&nbsp;</a></span>XAXIDMA_BD_START_CLEAR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_START_CLEAR&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Offset to start clear. </p>

</div>
</div>
<a id="ga83d7d4d6e88ab44910242b61fcd7f8fe"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga83d7d4d6e88ab44910242b61fcd7f8fe">&#9670;&nbsp;</a></span>XAXIDMA_BD_STRIDE_VSIZE_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET&#160;&#160;&#160;0x14</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>2D Transfer Sizes </p>

</div>
</div>
<a id="ga8018932d7e9b743c4c5c76ab3d373de1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8018932d7e9b743c4c5c76ab3d373de1">&#9670;&nbsp;</a></span>XAXIDMA_BD_STS_ALL_ERR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_STS_ALL_ERR_MASK&#160;&#160;&#160;0x70000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>All errors. </p>

</div>
</div>
<a id="gac433a776854849cbeaadcbed14132cb6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac433a776854849cbeaadcbed14132cb6">&#9670;&nbsp;</a></span>XAXIDMA_BD_STS_ALL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_STS_ALL_MASK&#160;&#160;&#160;0xFC000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>All status bits. </p>

</div>
</div>
<a id="gadb7c73caf5e5007dcb56ea029d7390ba"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadb7c73caf5e5007dcb56ea029d7390ba">&#9670;&nbsp;</a></span>XAXIDMA_BD_STS_COMPLETE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_STS_COMPLETE_MASK&#160;&#160;&#160;0x80000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Completed. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>

</div>
</div>
<a id="gae79c77f87a9887510ea53480c1e9a998"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae79c77f87a9887510ea53480c1e9a998">&#9670;&nbsp;</a></span>XAXIDMA_BD_STS_DEC_ERR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_STS_DEC_ERR_MASK&#160;&#160;&#160;0x40000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Decode error. </p>

</div>
</div>
<a id="ga09e502148e375f2d695d6d5d6e1797d2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga09e502148e375f2d695d6d5d6e1797d2">&#9670;&nbsp;</a></span>XAXIDMA_BD_STS_INT_ERR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_STS_INT_ERR_MASK&#160;&#160;&#160;0x10000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Internal err. </p>

</div>
</div>
<a id="gac71ad6cd79fc11e699bc10e3736fa08c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac71ad6cd79fc11e699bc10e3736fa08c">&#9670;&nbsp;</a></span>XAXIDMA_BD_STS_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_STS_OFFSET&#160;&#160;&#160;0x1C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Status. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>

</div>
</div>
<a id="ga91b0504c621f6c06b0df4752fe65ee3a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga91b0504c621f6c06b0df4752fe65ee3a">&#9670;&nbsp;</a></span>XAXIDMA_BD_STS_RXEOF_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_STS_RXEOF_MASK&#160;&#160;&#160;0x04000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Last rx pkt. </p>

</div>
</div>
<a id="ga29915484fd9f840a8ab727cf83bbfe81"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga29915484fd9f840a8ab727cf83bbfe81">&#9670;&nbsp;</a></span>XAXIDMA_BD_STS_RXSOF_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_STS_RXSOF_MASK&#160;&#160;&#160;0x08000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>First rx pkt. </p>

</div>
</div>
<a id="ga1f7727fc139a6b3100a5a17cb110efa6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1f7727fc139a6b3100a5a17cb110efa6">&#9670;&nbsp;</a></span>XAXIDMA_BD_STS_SLV_ERR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_STS_SLV_ERR_MASK&#160;&#160;&#160;0x20000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Slave error. </p>

</div>
</div>
<a id="gace0f0376ed9e0aad3d3e3c80254b20b4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gace0f0376ed9e0aad3d3e3c80254b20b4">&#9670;&nbsp;</a></span>XAXIDMA_BD_USR0_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_USR0_OFFSET&#160;&#160;&#160;0x20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>User IP specific word0. </p>

</div>
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<a id="ga7d9d62be0e0ed11b18f185b62dc72f67"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7d9d62be0e0ed11b18f185b62dc72f67">&#9670;&nbsp;</a></span>XAXIDMA_BD_USR1_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_USR1_OFFSET&#160;&#160;&#160;0x24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>User IP specific word1. </p>

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<a id="gadc83ff22099fdf61a5237965ce082504"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadc83ff22099fdf61a5237965ce082504">&#9670;&nbsp;</a></span>XAXIDMA_BD_USR2_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_USR2_OFFSET&#160;&#160;&#160;0x28</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>User IP specific word2. </p>

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<a id="gae1c5981447fe5ac113a6da3c1e19d6ed"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae1c5981447fe5ac113a6da3c1e19d6ed">&#9670;&nbsp;</a></span>XAXIDMA_BD_USR3_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_USR3_OFFSET&#160;&#160;&#160;0x2C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>User IP specific word3. </p>

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<a id="ga1ccae584923d0b6d0851a8bbae4528c9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1ccae584923d0b6d0851a8bbae4528c9">&#9670;&nbsp;</a></span>XAXIDMA_BD_USR4_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_USR4_OFFSET&#160;&#160;&#160;0x30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>User IP specific word4. </p>

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<a id="gafcbd1a131c650a5d6ceee6be15008a77"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gafcbd1a131c650a5d6ceee6be15008a77">&#9670;&nbsp;</a></span>XAXIDMA_BD_WORDLEN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_WORDLEN_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Whether has DRE mask. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>.</p>

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<a id="ga3db5b1d09deab9660ff65c06136acbc5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3db5b1d09deab9660ff65c06136acbc5">&#9670;&nbsp;</a></span>XAXIDMA_BD_WORDLEN_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BD_WORDLEN_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Whether has DRE shift. </p>

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<a id="ga86ffdcf7973d9648a0f4a4079f5d6e92"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga86ffdcf7973d9648a0f4a4079f5d6e92">&#9670;&nbsp;</a></span>XAxiDma_BdClear</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdClear</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">memset((<span class="keywordtype">void</span> *)(((UINTPTR)(BdPtr)) + <a class="code" href="group__axidma__v9__0.html#ga9eac2b100bcdf0aa763d1575f43c822b">XAXIDMA_BD_START_CLEAR</a>), 0, \</div><div class="line">    <a class="code" href="group__axidma__v9__0.html#ga97ec6974f990aef9ea2298c1df5d72c3">XAXIDMA_BD_BYTES_TO_CLEAR</a>)</div><div class="ttc" id="group__axidma__v9__0_html_ga97ec6974f990aef9ea2298c1df5d72c3"><div class="ttname"><a href="group__axidma__v9__0.html#ga97ec6974f990aef9ea2298c1df5d72c3">XAXIDMA_BD_BYTES_TO_CLEAR</a></div><div class="ttdeci">#define XAXIDMA_BD_BYTES_TO_CLEAR</div><div class="ttdoc">BD specific bytes to be cleared. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:247</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga9eac2b100bcdf0aa763d1575f43c822b"><div class="ttname"><a href="group__axidma__v9__0.html#ga9eac2b100bcdf0aa763d1575f43c822b">XAXIDMA_BD_START_CLEAR</a></div><div class="ttdeci">#define XAXIDMA_BD_START_CLEAR</div><div class="ttdoc">Offset to start clear. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:246</div></div>
</div><!-- fragment -->
<p>Zero out BD specific fields. </p>
<p>BD fields that are for the BD ring or for the system hardware build information are not touched.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga86ffdcf7973d9648a0f4a4079f5d6e92" title="Zero out BD specific fields. ">XAxiDma_BdClear(XAxiDma_Bd* BdPtr)</a> </dd></dl>

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<a id="gaae88a4ef129d6100fd087f7693186d80"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaae88a4ef129d6100fd087f7693186d80">&#9670;&nbsp;</a></span>XAxiDma_BdGetActualLength</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdGetActualLength</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">LengthMask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>) &amp; \</div><div class="line">                LengthMask)</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
</div><!-- fragment -->
<p>Get the actual transfer length of a BD. </p>
<p>The BD has completed in hw.</p>
<p>This function may not work if the BD is in cached memory.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to check on </td></tr>
    <tr><td class="paramname">LengthMask</td><td>is the Maximum Transfer Length.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#gaae88a4ef129d6100fd087f7693186d80" title="Get the actual transfer length of a BD. ">XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr)</a> </dd></dl>

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<a id="gaa5f7ba67cbbb678662e4b5d36c63d16e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa5f7ba67cbbb678662e4b5d36c63d16e">&#9670;&nbsp;</a></span>XAxiDma_BdGetARCache</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdGetARCache</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>)) &amp;  \</div><div class="line">                XAXIDMA_BD_ARCACHE_FIELD_MASK)</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
</div><!-- fragment -->
<p>Retrieve the ARCACHE field of the given BD previously set with XAxiDma_BdSetARCache. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gaa5f7ba67cbbb678662e4b5d36c63d16e" title="Retrieve the ARCACHE field of the given BD previously set with XAxiDma_BdSetARCache. ">XAxiDma_BdGetARCache(XAxiDma_Bd* BdPtr)</a> </dd></dl>

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<a id="ga72d1616af8d996f12db78473a75b54b6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga72d1616af8d996f12db78473a75b54b6">&#9670;&nbsp;</a></span>XAxiDma_BdGetARUser</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdGetARUser</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>)) &amp;  \</div><div class="line">                XAXIDMA_BD_ARUSER_FIELD_MASK)</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
</div><!-- fragment -->
<p>Retrieve the ARUSER field of the given BD previously set with XAxiDma_BdSetARUser. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga72d1616af8d996f12db78473a75b54b6" title="Retrieve the ARUSER field of the given BD previously set with XAxiDma_BdSetARUser. ">XAxiDma_BdGetARUser(XAxiDma_Bd* BdPtr)</a> </dd></dl>

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<a id="gab7295cfd7835998272435a39b656bf1f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab7295cfd7835998272435a39b656bf1f">&#9670;&nbsp;</a></span>XAxiDma_BdGetBufAddr</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdGetBufAddr</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td>&#160;&#160;&#160;(<a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">XAXIDMA_BD_BUFA_OFFSET</a>))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>

<p>Get the BD's buffer address. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gab7295cfd7835998272435a39b656bf1f" title="Get the BD&#39;s buffer address. ">XAxiDma_BdGetBufAddr(XAxiDma_Bd* BdPtr)</a> </dd></dl>

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<a id="ga495e780d704ecf548d3536b3bb8961a5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga495e780d704ecf548d3536b3bb8961a5">&#9670;&nbsp;</a></span>XAxiDma_BdGetCtrl</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdGetCtrl</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>)    \</div><div class="line">                &amp; <a class="code" href="group__axidma__v9__0.html#gaa409dba5ec46ad5a31953e22c4d3333f">XAXIDMA_BD_CTRL_ALL_MASK</a>)</div><div class="ttc" id="group__axidma__v9__0_html_gac3372d0a1625537d5b637f40ca20f52c"><div class="ttname"><a href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_CTRL_LEN_OFFSET</div><div class="ttdoc">Control/buffer length. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:227</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gaa409dba5ec46ad5a31953e22c4d3333f"><div class="ttname"><a href="group__axidma__v9__0.html#gaa409dba5ec46ad5a31953e22c4d3333f">XAXIDMA_BD_CTRL_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_BD_CTRL_ALL_MASK</div><div class="ttdoc">All control bits. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:268</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
</div><!-- fragment -->
<p>Get the control bits for the BD. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The bit mask for the control of the BD</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga495e780d704ecf548d3536b3bb8961a5" title="Get the control bits for the BD. ">XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>

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<a id="gaf3f333d78d115724bfcac84746d8cfa6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf3f333d78d115724bfcac84746d8cfa6">&#9670;&nbsp;</a></span>XAxiDma_BdGetId</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdGetId</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td>&#160;&#160;&#160;(<a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">XAXIDMA_BD_ID_OFFSET</a>))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>

<p>Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gaf3f333d78d115724bfcac84746d8cfa6" title="Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId. ">XAxiDma_BdGetId(XAxiDma_Bd* BdPtr)</a> </dd></dl>

</div>
</div>
<a id="gadaf226acada2c1d857d29205ce4c2a58"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadaf226acada2c1d857d29205ce4c2a58">&#9670;&nbsp;</a></span>XAxiDma_BdGetLength</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdGetLength</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">LengthMask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>) &amp; \</div><div class="line">                LengthMask)</div><div class="ttc" id="group__axidma__v9__0_html_gac3372d0a1625537d5b637f40ca20f52c"><div class="ttname"><a href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_CTRL_LEN_OFFSET</div><div class="ttdoc">Control/buffer length. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:227</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
</div><!-- fragment -->
<p>Retrieve the length field value from the given BD. </p>
<p>The returned value is the same as what was written with <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07" title="Set the length field for the given BD. ">XAxiDma_BdSetLength()</a>. Note that in the this value does not reflect the real length of received data. See the comments of <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07" title="Set the length field for the given BD. ">XAxiDma_BdSetLength()</a> for more details. To obtain the actual transfer length, use <a class="el" href="group__axidma__v9__0.html#gaae88a4ef129d6100fd087f7693186d80" title="Get the actual transfer length of a BD. ">XAxiDma_BdGetActualLength()</a>.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on. </td></tr>
    <tr><td class="paramname">LengthMask</td><td>is the Maximum Transfer Length.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The length value set in the BD.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gadaf226acada2c1d857d29205ce4c2a58" title="Retrieve the length field value from the given BD. ">XAxiDma_BdGetLength(XAxiDma_Bd* BdPtr)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>

</div>
</div>
<a id="ga29a75b8f1de16a347544e37b48d8129c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga29a75b8f1de16a347544e37b48d8129c">&#9670;&nbsp;</a></span>XAxiDma_BdGetStride</h2>

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          <td class="memname">#define XAxiDma_BdGetStride</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>)) &amp;  \</div><div class="line">                XAXIDMA_BD_STRIDE_FIELD_MASK)</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga83d7d4d6e88ab44910242b61fcd7f8fe"><div class="ttname"><a href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET</div><div class="ttdoc">2D Transfer Sizes </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:226</div></div>
</div><!-- fragment -->
<p>Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetStride. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga29a75b8f1de16a347544e37b48d8129c" title="Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetStride. ">XAxiDma_BdGetStride(XAxiDma_Bd* BdPtr)</a> </dd></dl>

</div>
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<a id="ga8a0271e5255b139cc63e08e46b9c473a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8a0271e5255b139cc63e08e46b9c473a">&#9670;&nbsp;</a></span>XAxiDma_BdGetSts</h2>

<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdGetSts</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>) &amp; \</div><div class="line">                XAXIDMA_BD_STS_ALL_MASK)</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
</div><!-- fragment -->
<p>Retrieve the status of a BD. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Word at offset XAXIDMA_BD_DMASR_OFFSET. Use XAXIDMA_BD_STS_*** values defined in <a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a> to interpret the returned value</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga8a0271e5255b139cc63e08e46b9c473a" title="Retrieve the status of a BD. ">XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>

</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8c1e3dd04821568424ffc77caf11a851">&#9670;&nbsp;</a></span>XAxiDma_BdGetTDest</h2>

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      <table class="memname">
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          <td class="memname">#define XAxiDma_BdGetTDest</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>)) &amp;  \</div><div class="line">                XAXIDMA_BD_TDEST_FIELD_MASK)</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
</div><!-- fragment -->
<p>Retrieve the TDest field of the RX BD previously set with i XAxiDma_BdSetTDest. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga8c1e3dd04821568424ffc77caf11a851" title="Retrieve the TDest field of the RX BD previously set with i XAxiDma_BdSetTDest. ">XAxiDma_BdGetTDest(XAxiDma_Bd* BdPtr)</a> </dd></dl>

</div>
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<a id="gac14fa76311fd7e5fb59b81fd9e251f62"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac14fa76311fd7e5fb59b81fd9e251f62">&#9670;&nbsp;</a></span>XAxiDma_BdGetTId</h2>

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          <td class="memname">#define XAxiDma_BdGetTId</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>)) &amp;  \</div><div class="line">                XAXIDMA_BD_TID_FIELD_MASK)</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
</div><!-- fragment -->
<p>Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gac14fa76311fd7e5fb59b81fd9e251f62" title="Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId. ">XAxiDma_BdGetTId(XAxiDma_Bd* BdPtr)</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga7a2f9668058b7e4cdc89dffcce6086d3">&#9670;&nbsp;</a></span>XAxiDma_BdGetTUser</h2>

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<div class="memproto">
      <table class="memname">
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          <td class="memname">#define XAxiDma_BdGetTUser</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>)) &amp;  \</div><div class="line">                XAXIDMA_BD_TUSER_FIELD_MASK)</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
</div><!-- fragment -->
<p>Retrieve the TUSER field of the RX BD previously set with XAxiDma_BdSetTUser. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga7a2f9668058b7e4cdc89dffcce6086d3" title="Retrieve the TUSER field of the RX BD previously set with XAxiDma_BdSetTUser. ">XAxiDma_BdGetTUser(XAxiDma_Bd* BdPtr)</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gad9f48ceb5b30d66bab23337edc35d2fe">&#9670;&nbsp;</a></span>XAxiDma_BdGetVSize</h2>

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          <td class="memname">#define XAxiDma_BdGetVSize</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>)) &amp;  \</div><div class="line">                XAXIDMA_BD_VSIZE_FIELD_MASK)</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga83d7d4d6e88ab44910242b61fcd7f8fe"><div class="ttname"><a href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET</div><div class="ttdoc">2D Transfer Sizes </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:226</div></div>
</div><!-- fragment -->
<p>Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetVSize. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gad9f48ceb5b30d66bab23337edc35d2fe" title="Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetVSize. ...">XAxiDma_BdGetVSize(XAxiDma_Bd* BdPtr)</a> </dd></dl>

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<a id="ga844fc6b60315598387d17c8148a891e4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga844fc6b60315598387d17c8148a891e4">&#9670;&nbsp;</a></span>XAxiDma_BdHwCompleted</h2>

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      <table class="memname">
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          <td class="memname">#define XAxiDma_BdHwCompleted</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>) &amp; \</div><div class="line">                XAXIDMA_BD_STS_COMPLETE_MASK)</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gac71ad6cd79fc11e699bc10e3736fa08c"><div class="ttname"><a href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STS_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:228</div></div>
</div><!-- fragment -->
<p>Check whether a BD has completed in hardware. </p>
<p>This BD has been submitted to hardware. The application can use this function to poll for the completion of the BD.</p>
<p>This function may not work if the BD is in cached memory.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to check on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>0 if not complete</li>
<li>XAXIDMA_BD_STS_COMPLETE_MASK if completed, may contain XAXIDMA_BD_STS_*_ERR_MASK bits.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#ga844fc6b60315598387d17c8148a891e4" title="Check whether a BD has completed in hardware. ">XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr)</a> </dd></dl>

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<a id="gaa738ffd392c7ae1e844fab340ba50fee"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa738ffd392c7ae1e844fab340ba50fee">&#9670;&nbsp;</a></span>XAxiDma_BdRead</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdRead</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(*(u32 *)(((void *)(UINTPTR)(BaseAddress)) + (u32)(Offset)))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>

<p>Read the given Buffer Descriptor word. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the BD to read </td></tr>
    <tr><td class="paramname">Offset</td><td>is the word offset to be read</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the field</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee" title="Read the given Buffer Descriptor word. ">XAxiDma_BdRead(u32 BaseAddress, u32 Offset)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga9d2814e4249884e68fe9e6f370920ca4">XAxiDma_BdGetAppWord()</a>, <a class="el" href="group__axidma__v9__0.html#gafc6434a23594c20c2b601f010a979e48">XAxiDma_BdSetAppWord()</a>, <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">XAxiDma_BdSetBufAddr()</a>, <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">XAxiDma_BdSetCtrl()</a>, and <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07">XAxiDma_BdSetLength()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga9e782e3715c1d2dd03e5d03434f47319">&#9670;&nbsp;</a></span>XAxiDma_BdRingAckIrq</h2>

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          <td class="memname">#define XAxiDma_BdRingAckIrq</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Mask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>,\</div><div class="line">                        (Mask) &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)</div><div class="ttc" id="group__axidma__v9__0_html_ga73dabf09bac8a209e0cc367f6ccdf44b"><div class="ttname"><a href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:349</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
</div><!-- fragment -->
<p>Acknowledge asserted interrupts. </p>
<p>It modifies XAXIDMA_SR_OFFSET register. A mask bit set for an unasserted interrupt has no effect.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on. </td></tr>
    <tr><td class="paramname">Mask</td><td>are the interrupt signals to acknowledge</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga9e782e3715c1d2dd03e5d03434f47319" title="Acknowledge asserted interrupts. ">XAxiDma_BdRingAckIrq(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>

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<a id="gaf7c291190c92ce93d72f95c5b04ef1d4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf7c291190c92ce93d72f95c5b04ef1d4">&#9670;&nbsp;</a></span>XAxiDma_BdRingBusy</h2>

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          <td class="memname">#define XAxiDma_BdRingBusy</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">XAxiDma_BdRingHwIsStarted</a>(RingPtr) &amp;&amp;          \</div><div class="line">                ((<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>) \</div><div class="line">                        &amp; <a class="code" href="group__axidma__v9__0.html#gaa3538e8c2a6e024641259c85368667f0">XAXIDMA_IDLE_MASK</a>) ? FALSE : TRUE))</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gaa3538e8c2a6e024641259c85368667f0"><div class="ttname"><a href="group__axidma__v9__0.html#gaa3538e8c2a6e024641259c85368667f0">XAXIDMA_IDLE_MASK</a></div><div class="ttdeci">#define XAXIDMA_IDLE_MASK</div><div class="ttdoc">DMA channel idle. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:173</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga766bed2454969636d827fb79faeeee97"><div class="ttname"><a href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">XAxiDma_BdRingHwIsStarted</a></div><div class="ttdeci">#define XAxiDma_BdRingHwIsStarted(RingPtr)</div><div class="ttdoc">Check whether a DMA channel is started, meaning the channel is not halted. </div><div class="ttdef"><b>Definition:</b> xaxidma_bdring.h:370</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
</div><!-- fragment -->
<p>Check if the current DMA channel is busy with a DMA operation. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>1 if the DMA is busy.</li>
<li>0 otherwise</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#gaf7c291190c92ce93d72f95c5b04ef1d4" title="Check if the current DMA channel is busy with a DMA operation. ">XAxiDma_BdRingBusy(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5c87fcb74fe669b5998e53d0a4b35127">&#9670;&nbsp;</a></span>XAxiDma_BdRingCntCalc</h2>

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      <table class="memname">
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          <td class="memname">#define XAxiDma_BdRingCntCalc</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Alignment, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Bytes&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(uint32_t)((Bytes)/((sizeof(<a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a>)+((Alignment)-1))&amp;~((Alignment)-1)))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>

<p>Use this macro at initialization time to determine how many BDs will fit within the given memory constraints. </p>
<p>The results of this macro can be provided to <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Alignment</td><td>specifies what byte alignment the BDs must fall on and must be a power of 2 to get an accurate calculation (32, 64, 126,...) </td></tr>
    <tr><td class="paramname">Bytes</td><td>is the number of bytes to be used to store BDs.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Number of BDs that can fit in the given memory area</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#ga5c87fcb74fe669b5998e53d0a4b35127" title="Use this macro at initialization time to determine how many BDs will fit within the given memory cons...">XAxiDma_BdRingCntCalc(u32 Alignment, u32 Bytes)</a> This function is used only when system is configured as SG mode </dd></dl>

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<a id="gac62389e25e6775026cf1be6c383e665b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac62389e25e6775026cf1be6c383e665b">&#9670;&nbsp;</a></span>XAxiDma_BdRingGetCnt</h2>

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        <tr>
          <td class="memname">#define XAxiDma_BdRingGetCnt</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr</td><td>)</td>
          <td>&#160;&#160;&#160;((RingPtr)-&gt;AllCnt)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>

<p>Return the total number of BDs allocated by this channel with <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the BD ring to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The total number of BDs allocated for this channel.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#gac62389e25e6775026cf1be6c383e665b" title="Return the total number of BDs allocated by this channel with XAxiDma_BdRingCreate(). ">XAxiDma_BdRingGetCnt(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gadd32e45591597a4bfa84b66dffc98913">&#9670;&nbsp;</a></span>XAxiDma_BdRingGetCurrBd</h2>

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          <td class="memname">#define XAxiDma_BdRingGetCurrBd</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *)<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, \</div><div class="line">                                        XAXIDMA_CDESC_OFFSET)              \</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga5faf4d844b10fc577f3a75a170f11867"><div class="ttname"><a href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a></div><div class="ttdeci">u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]</div><div class="ttdoc">The XAxiDma_Bd is the type for a buffer descriptor (BD). </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:136</div></div>
</div><!-- fragment -->
<p>Get the BD a BD ring is processing. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the BD ring to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The current BD that the BD ring is working on</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: XAxiDma_Bd * <a class="el" href="group__axidma__v9__0.html#gadd32e45591597a4bfa84b66dffc98913" title="Get the BD a BD ring is processing. ">XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>

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<a id="ga24cd47cdbfac0813e0d9caf966a1a3d2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga24cd47cdbfac0813e0d9caf966a1a3d2">&#9670;&nbsp;</a></span>XAxiDma_BdRingGetError</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdRingGetError</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>) \</div><div class="line">                        &amp; <a class="code" href="group__axidma__v9__0.html#ga4102192c408420feb5b7db14d47c6d5c">XAXIDMA_ERR_ALL_MASK</a>)</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga4102192c408420feb5b7db14d47c6d5c"><div class="ttname"><a href="group__axidma__v9__0.html#ga4102192c408420feb5b7db14d47c6d5c">XAXIDMA_ERR_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_ERR_ALL_MASK</div><div class="ttdoc">All errors. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:184</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
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<p>Get error bits of a DMA channel. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Rrror bits in the status register, they should be interpreted with XAXIDMA_ERR_*_MASK defined in <a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a></dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga24cd47cdbfac0813e0d9caf966a1a3d2" title="Get error bits of a DMA channel. ">XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>

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<a id="ga415cf0c379fef0104f9f52881ead13a7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga415cf0c379fef0104f9f52881ead13a7">&#9670;&nbsp;</a></span>XAxiDma_BdRingGetFreeCnt</h2>

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        <tr>
          <td class="memname">#define XAxiDma_BdRingGetFreeCnt</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr</td><td>)</td>
          <td>&#160;&#160;&#160;((RingPtr)-&gt;FreeCnt)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>

<p>Return the number of BDs allocatable with <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a> for pre- processing. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the BD ring to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The number of BDs currently allocatable.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#ga415cf0c379fef0104f9f52881ead13a7" title="Return the number of BDs allocatable with XAxiDma_BdRingAlloc() for pre- processing. ">XAxiDma_BdRingGetFreeCnt(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga7a9d2103e6d09fc3850b34a6386dc803">&#9670;&nbsp;</a></span>XAxiDma_BdRingGetIrq</h2>

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          <td class="memname">#define XAxiDma_BdRingGetIrq</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>) \</div><div class="line">                        &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
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<p>Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET. </p>
<p>This operation can be used to see which interrupts are pending.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Current contents of the IRQ_OFFSET register. Use XAXIDMA_IRQ_*** values defined in <a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a> to interpret the returned value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga7a9d2103e6d09fc3850b34a6386dc803" title="Retrieve the contents of the channel&#39;s IRQ register XAXIDMA_SR_OFFSET. ">XAxiDma_BdRingGetIrq(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>

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<a id="ga740fa349c7811de2b7bae5cf83eb445e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga740fa349c7811de2b7bae5cf83eb445e">&#9670;&nbsp;</a></span>XAxiDma_BdRingGetSr</h2>

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        <tr>
          <td class="memname">#define XAxiDma_BdRingGetSr</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr</td><td>)</td>
          <td>&#160;&#160;&#160;<a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>

<p>Retrieve the contents of the channel status register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Current contents of status register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#ga740fa349c7811de2b7bae5cf83eb445e" title="Retrieve the contents of the channel status register. ">XAxiDma_BdRingGetSr(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga766bed2454969636d827fb79faeeee97">&#9670;&nbsp;</a></span>XAxiDma_BdRingHwIsStarted</h2>

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      <table class="memname">
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          <td class="memname">#define XAxiDma_BdRingHwIsStarted</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>) \</div><div class="line">                        &amp; <a class="code" href="group__axidma__v9__0.html#ga70671c3d8cd1e51c56723e298d268cce">XAXIDMA_HALTED_MASK</a>) ? FALSE : TRUE)</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga70671c3d8cd1e51c56723e298d268cce"><div class="ttname"><a href="group__axidma__v9__0.html#ga70671c3d8cd1e51c56723e298d268cce">XAXIDMA_HALTED_MASK</a></div><div class="ttdeci">#define XAXIDMA_HALTED_MASK</div><div class="ttdoc">DMA channel halted. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:172</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
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<p>Check whether a DMA channel is started, meaning the channel is not halted. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>1 if channel is started</li>
<li>0 otherwise</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97" title="Check whether a DMA channel is started, meaning the channel is not halted. ">XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>

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<a id="ga0269e07693c731cf7721c6f19f8eb69b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0269e07693c731cf7721c6f19f8eb69b">&#9670;&nbsp;</a></span>XAxiDma_BdRingIntDisable</h2>

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          <td class="memname">#define XAxiDma_BdRingIntDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Mask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, \</div><div class="line">                <a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>) &amp; \</div><div class="line">                        ~((Mask) &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)))</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga73dabf09bac8a209e0cc367f6ccdf44b"><div class="ttname"><a href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:349</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
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<p>Clear interrupt enable bits for a channel. </p>
<p>It modifies the XAXIDMA_CR_OFFSET register.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on. </td></tr>
    <tr><td class="paramname">Mask</td><td>consists of the interrupt signals to disable.Bits not specified in the Mask are not affected.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr, u32 Mask) This function is used only when system is configured as SG mode </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2518030938ab80081f6896fc5589682c">&#9670;&nbsp;</a></span>XAxiDma_BdRingIntEnable</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdRingIntEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Mask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, \</div><div class="line">                <a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>) \</div><div class="line">                        | ((Mask) &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)))</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga73dabf09bac8a209e0cc367f6ccdf44b"><div class="ttname"><a href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:349</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
</div><!-- fragment -->
<p>Set interrupt enable bits for a channel. </p>
<p>This operation will modify the XAXIDMA_CR_OFFSET register.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on. </td></tr>
    <tr><td class="paramname">Mask</td><td>consists of the interrupt signals to enable.Bits not specified in the mask are not affected.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga2518030938ab80081f6896fc5589682c" title="Set interrupt enable bits for a channel. ">XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)</a> This function is used only when system is configured as SG mode </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gadbb17169213d8af8b50e6dee7f7b6d8b">&#9670;&nbsp;</a></span>XAxiDma_BdRingIntGetEnabled</h2>

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<div class="memproto">
      <table class="memname">
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          <td class="memname">#define XAxiDma_BdRingIntGetEnabled</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>) \</div><div class="line">                &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
</div><!-- fragment -->
<p>Get enabled interrupts of a channel. </p>
<p>It is in XAXIDMA_CR_OFFSET register.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the channel instance to operate on. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Enabled interrupts of a channel. Use XAXIDMA_IRQ_* defined in <a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a> to interpret this returned value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gadbb17169213d8af8b50e6dee7f7b6d8b" title="Get enabled interrupts of a channel. ">XAxiDma_BdRingIntGetEnabled(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga6899085c400b8f453381b305ac5521d9">&#9670;&nbsp;</a></span>XAxiDma_BdRingMemCalc</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdRingMemCalc</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Alignment, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">NumBd&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(int)((sizeof(<a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a>)+((Alignment)-1)) &amp; ~((Alignment)-1))*(NumBd)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>

<p>Use this macro at initialization time to determine how many bytes of memory are required to contain a given number of BDs at a given alignment. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Alignment</td><td>specifies what byte alignment the BDs must fall on. This parameter must be a power of 2 to get an accurate calculation (32, 64,128,...) </td></tr>
    <tr><td class="paramname">NumBd</td><td>is the number of BDs to calculate memory size requirements</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The number of bytes of memory required to create a BD list with the given memory constraints.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: int <a class="el" href="group__axidma__v9__0.html#ga6899085c400b8f453381b305ac5521d9" title="Use this macro at initialization time to determine how many bytes of memory are required to contain a...">XAxiDma_BdRingMemCalc(u32 Alignment, u32 NumBd)</a> This function is used only when system is configured as SG mode </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga4b7e75d1acf86428bd79fcd0d1c13745">&#9670;&nbsp;</a></span>XAxiDma_BdRingNext</h2>

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        <tr>
          <td class="memname">#define XAxiDma_BdRingNext</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(((UINTPTR)(BdPtr) &gt;= (RingPtr)-&gt;LastBdAddr) ?  \</div><div class="line">                        (UINTPTR)(RingPtr)-&gt;FirstBdAddr :       \</div><div class="line">                        (UINTPTR)((UINTPTR)(BdPtr) + (RingPtr)-&gt;Separation))</div></div><!-- fragment -->
<p>Return the next BD in the ring. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the BD ring to operate on. </td></tr>
    <tr><td class="paramname">BdPtr</td><td>is the current BD.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The next BD in the ring relative to the BdPtr parameter.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: XAxiDma_Bd <em>XAxiDma_BdRingNext(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a></em> RingPtr, XAxiDma_Bd *BdPtr) This function is used only when system is configured as SG mode </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga86c6d4b9c4f8766634d46a3078eadc8a">&#9670;&nbsp;</a></span>XAxiDma_BdRingPrev</h2>

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        <tr>
          <td class="memname">#define XAxiDma_BdRingPrev</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(((u32)(BdPtr) &lt;= (RingPtr)-&gt;FirstBdAddr) ?             \</div><div class="line">                        (<a class="code" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a>*)(RingPtr)-&gt;LastBdAddr :            \</div><div class="line">                        (<a class="code" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a>*)((u32)(BdPtr) - (RingPtr)-&gt;Separation))</div><div class="ttc" id="group__axidma__v9__0_html_ga5faf4d844b10fc577f3a75a170f11867"><div class="ttname"><a href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a></div><div class="ttdeci">u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]</div><div class="ttdoc">The XAxiDma_Bd is the type for a buffer descriptor (BD). </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:136</div></div>
</div><!-- fragment -->
<p>Return the previous BD in the ring. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the DMA channel to operate on. </td></tr>
    <tr><td class="paramname">BdPtr</td><td>is the current BD.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The previous BD in the ring relative to the BdPtr parameter.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: XAxiDma_Bd <em>XAxiDma_BdRingPrev(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a></em> RingPtr, XAxiDma_Bd *BdPtr) This function is used only when system is configured as SG mode </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0d79253861939c76e6d440ecde2b6edd">&#9670;&nbsp;</a></span>XAxiDma_BdRingSnapShotCurrBd</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdRingSnapShotCurrBd</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingPtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8h.html">xaxidma_bdring.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">{                                                                 \</div><div class="line">                if (!RingPtr-&gt;IsRxChannel) {                              \</div><div class="line">                        (RingPtr)-&gt;BdaRestart =                           \</div><div class="line">                                (<a class="code" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *)(UINTPTR)<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>(           \</div><div class="line">                                        (RingPtr)-&gt;ChanBase,              \</div><div class="line">                                        XAXIDMA_CDESC_OFFSET);            \</div><div class="line">                } <span class="keywordflow">else</span> {                                                  \</div><div class="line">                        if (!RingPtr-&gt;RingIndex) {                                \</div><div class="line">                                (RingPtr)-&gt;BdaRestart =                   \</div><div class="line">                                (<a class="code" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *)(UINTPTR)<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>(            \</div><div class="line">                                        (RingPtr)-&gt;ChanBase,              \</div><div class="line">                                        XAXIDMA_CDESC_OFFSET);            \</div><div class="line">                        } <span class="keywordflow">else</span> {                                          \</div><div class="line">                                (RingPtr)-&gt;BdaRestart =                   \</div><div class="line">                                (<a class="code" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *)(UINTPTR)<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>(                   \</div><div class="line">                                (RingPtr)-&gt;ChanBase,                      \</div><div class="line">                                (<a class="code" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">XAXIDMA_RX_CDESC0_OFFSET</a> +               \</div><div class="line">                                (RingPtr-&gt;RingIndex - 1) *                \</div><div class="line">                                        <a class="code" href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">XAXIDMA_RX_NDESC_OFFSET</a>));        \</div><div class="line">                        }                                                 \</div><div class="line">                }                                                         \</div><div class="line">        }</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga5faf4d844b10fc577f3a75a170f11867"><div class="ttname"><a href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a></div><div class="ttdeci">u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]</div><div class="ttdoc">The XAxiDma_Bd is the type for a buffer descriptor (BD). </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:136</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga6fc559cbc93b62195de6ecaf25492467"><div class="ttname"><a href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">XAXIDMA_RX_NDESC_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_NDESC_OFFSET</div><div class="ttdoc">Rx Next Descriptor Offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:148</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga79d2eca90f2554b8c893b2f9a70c795c"><div class="ttname"><a href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">XAXIDMA_RX_CDESC0_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_CDESC0_OFFSET</div><div class="ttdoc">Multi-Channel DMA Descriptor Offsets. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:144</div></div>
</div><!-- fragment -->
<p>Snap shot the latest BD a BD ring is processing. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the BD ring to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga0d79253861939c76e6d440ecde2b6edd" title="Snap shot the latest BD a BD ring is processing. ">XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing* RingPtr)</a> This function is used only when system is configured as SG mode </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gac7d8a383cd6d5aff6ee36c3a3db20cbf">&#9670;&nbsp;</a></span>XAxiDma_BdSetARCache</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdSetARCache</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">ARCache&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">{ \</div><div class="line">        u32 val; \</div><div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>) &amp; \</div><div class="line">                ~XAXIDMA_BD_ARCACHE_FIELD_MASK); \</div><div class="line">        val |= ((u32)(ARCache) &lt;&lt; XAXIDMA_BD_ARCACHE_FIELD_SHIFT); \</div><div class="line">        XAxiDma_BdWrite((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>, val); \</div><div class="line">}</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
</div><!-- fragment -->
<p>Set the ARCACHE field of the given BD. </p>
<p>This signal provides additional information about the cacheable characteristics of the transfer.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
    <tr><td class="paramname">ARCache</td><td>is a 8 bit quantity to set in the BD</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#gac7d8a383cd6d5aff6ee36c3a3db20cbf" title="Set the ARCACHE field of the given BD. ">XAxiDma_BdSetARCache(XAxiDma_Bd* BdPtr, void ARCache)</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gae89253197f1aef6582d5cda3e49f8ead">&#9670;&nbsp;</a></span>XAxiDma_BdSetARUser</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdSetARUser</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">ARUser&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">{ \</div><div class="line">        u32 val; \</div><div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>) &amp; \</div><div class="line">                ~XAXIDMA_BD_ARUSER_FIELD_MASK); \</div><div class="line">        val |= ((u32)(ARUser) &lt;&lt; XAXIDMA_BD_ARUSER_FIELD_SHIFT); \</div><div class="line">        XAxiDma_BdWrite((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>, val); \</div><div class="line">}</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
</div><!-- fragment -->
<p>Set the ARUSER field of the given BD. </p>
<p>Sideband signals used for user defined information.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
    <tr><td class="paramname">ARUser</td><td>is a 8 bit quantity to set in the BD</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#gae89253197f1aef6582d5cda3e49f8ead" title="Set the ARUSER field of the given BD. ">XAxiDma_BdSetARUser(XAxiDma_Bd* BdPtr, void ARUser)</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga3d935ef5d41f72d0d57a15aaf5928062">&#9670;&nbsp;</a></span>XAxiDma_BdSetId</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdSetId</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Id&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(<a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>((BdPtr), <a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">XAXIDMA_BD_ID_OFFSET</a>, (u32)(Id)))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>

<p>Set the ID field of the given BD. </p>
<p>The ID is an arbitrary piece of data the application can associate with a specific BD.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
    <tr><td class="paramname">Id</td><td>is a 32 bit quantity to set in the BD</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga3d935ef5d41f72d0d57a15aaf5928062" title="Set the ID field of the given BD. ">XAxiDma_BdSetId(XAxiDma_Bd* BdPtr, void Id)</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga58961be41e3c0bc2694444bfe37b6c27">&#9670;&nbsp;</a></span>XAxiDma_BdSetStride</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdSetStride</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Stride&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">{ \</div><div class="line">        u32 val; \</div><div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>) &amp; \</div><div class="line">                ~XAXIDMA_BD_STRIDE_FIELD_MASK); \</div><div class="line">        val |= ((u32)(Stride) &lt;&lt; XAXIDMA_BD_STRIDE_FIELD_SHIFT); \</div><div class="line">        XAxiDma_BdWrite((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>, val); \</div><div class="line">}</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga83d7d4d6e88ab44910242b61fcd7f8fe"><div class="ttname"><a href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET</div><div class="ttdoc">2D Transfer Sizes </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:226</div></div>
</div><!-- fragment -->
<p>Set the STRIDE field of the given BD. </p>
<p>It is the address distance between the first address of successive horizontal reads.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
    <tr><td class="paramname">Stride</td><td>is a 32 bit quantity to set in the BD</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga58961be41e3c0bc2694444bfe37b6c27" title="Set the STRIDE field of the given BD. ">XAxiDma_BdSetStride(XAxiDma_Bd* BdPtr, void Stride)</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5f9b3088c4e16c7f5584610a43b17462">&#9670;&nbsp;</a></span>XAxiDma_BdSetTDest</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdSetTDest</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">TDest&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">{ \</div><div class="line">        u32 val; \</div><div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>) &amp; \</div><div class="line">                ~XAXIDMA_BD_TDEST_FIELD_MASK); \</div><div class="line">        val |= ((u32)(TDest) &lt;&lt; XAXIDMA_BD_TDEST_FIELD_SHIFT); \</div><div class="line">        XAxiDma_BdWrite((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>, val); \</div><div class="line">}</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
</div><!-- fragment -->
<p>Set the TDEST field of the TX BD. </p>
<p>Provides coarse routing information for the data stream.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
    <tr><td class="paramname">TDest</td><td>is a 8 bit quantity to set in the BD</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga5f9b3088c4e16c7f5584610a43b17462" title="Set the TDEST field of the TX BD. ">XAxiDma_BdSetTDest(XAxiDma_Bd* BdPtr, void TDest)</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gaa5bc321894b77ca6194c867018d9fe12">&#9670;&nbsp;</a></span>XAxiDma_BdSetTId</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdSetTId</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">TId&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">{ \</div><div class="line">        u32 val; \</div><div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>) &amp; \</div><div class="line">                ~XAXIDMA_BD_TID_FIELD_MASK); \</div><div class="line">        val |= ((u32)(TId) &lt;&lt; XAXIDMA_BD_TID_FIELD_SHIFT); \</div><div class="line">        XAxiDma_BdWrite((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>, val); \</div><div class="line">}</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
</div><!-- fragment -->
<p>Set the TID field of the TX BD. </p>
<p>Provides a stream identifier and can be used to differentiate between multiple streams of data that are being transferred across the same interface.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
    <tr><td class="paramname">TId</td><td>is a 8 bit quantity to set in the BD</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#gaa5bc321894b77ca6194c867018d9fe12" title="Set the TID field of the TX BD. ">XAxiDma_BdSetTId(XAxiDma_Bd* BdPtr, void TId)</a> </dd></dl>

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<a id="gacf41c0ebe00870b6cdd34e46698e081b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gacf41c0ebe00870b6cdd34e46698e081b">&#9670;&nbsp;</a></span>XAxiDma_BdSetTUser</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdSetTUser</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">TUser&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">{ \</div><div class="line">        u32 val; \</div><div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>) &amp; \</div><div class="line">                ~XAXIDMA_BD_TUSER_FIELD_MASK); \</div><div class="line">        val |= ((u32)(TUser) &lt;&lt; XAXIDMA_BD_TUSER_FIELD_SHIFT); \</div><div class="line">        XAxiDma_BdWrite((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a>, val); \</div><div class="line">}</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga6daf74c6d99207a0d8ba91a049e661c6"><div class="ttname"><a href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">XAXIDMA_BD_MCCTL_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_MCCTL_OFFSET</div><div class="ttdoc">Multichannel Control Fields. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:225</div></div>
</div><!-- fragment -->
<p>Set the TUSER field of the TX BD. </p>
<p>User defined sideband signaling.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
    <tr><td class="paramname">TUser</td><td>is a 8 bit quantity to set in the BD</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#gacf41c0ebe00870b6cdd34e46698e081b" title="Set the TUSER field of the TX BD. ">XAxiDma_BdSetTUser(XAxiDma_Bd* BdPtr, void TUser)</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga383b2c0667bf5bafa22922168895bd5e">&#9670;&nbsp;</a></span>XAxiDma_BdSetVSize</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdSetVSize</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BdPtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">VSize&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">{ \</div><div class="line">        u32 val; \</div><div class="line">        val = (<a class="code" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>) &amp; \</div><div class="line">                ~XAXIDMA_BD_VSIZE_FIELD_MASK); \</div><div class="line">        val |= ((u32)(VSize) &lt;&lt; XAXIDMA_BD_VSIZE_FIELD_SHIFT); \</div><div class="line">        XAxiDma_BdWrite((BdPtr), <a class="code" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a>, val); \</div><div class="line">}</div><div class="ttc" id="group__axidma__v9__0_html_gaa738ffd392c7ae1e844fab340ba50fee"><div class="ttname"><a href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a></div><div class="ttdeci">#define XAxiDma_BdRead(BaseAddress, Offset)</div><div class="ttdoc">Read the given Buffer Descriptor word. </div><div class="ttdef"><b>Definition:</b> xaxidma_bd.h:171</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga83d7d4d6e88ab44910242b61fcd7f8fe"><div class="ttname"><a href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">XAXIDMA_BD_STRIDE_VSIZE_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET</div><div class="ttdoc">2D Transfer Sizes </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:226</div></div>
</div><!-- fragment -->
<p>Set the VSIZE field of the given BD. </p>
<p>Number of horizontal lines for strided access.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
    <tr><td class="paramname">VSize</td><td>is a 32 bit quantity to set in the BD</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga383b2c0667bf5bafa22922168895bd5e" title="Set the VSIZE field of the given BD. ">XAxiDma_BdSetVSize(XAxiDma_Bd* BdPtr, void VSize)</a> </dd></dl>

</div>
</div>
<a id="gab3b7d771208c01701b35bce165332a9f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab3b7d771208c01701b35bce165332a9f">&#9670;&nbsp;</a></span>XAxiDma_BdWrite</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdWrite</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>

<p>Write the given Buffer Descriptor word. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the BD to write </td></tr>
    <tr><td class="paramname">Offset</td><td>is the word offset to be written </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the field</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f" title="Write the given Buffer Descriptor word. ">XAxiDma_BdWrite(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">XAxiDma_BdSetCtrl()</a>, and <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07">XAxiDma_BdSetLength()</a>.</p>

</div>
</div>
<a id="ga273953f607ecfa92d879c4ee3660f954"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga273953f607ecfa92d879c4ee3660f954">&#9670;&nbsp;</a></span>XAxiDma_BdWrite64</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_BdWrite64</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(*(u64 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u64)(Data)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>

<p>Write the given Buffer Descriptor word. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the BD to write </td></tr>
    <tr><td class="paramname">Offset</td><td>is the word offset to be written </td></tr>
    <tr><td class="paramname">Data</td><td>is the 64-bit value to write to the field</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f" title="Write the given Buffer Descriptor word. ">XAxiDma_BdWrite(u64 BaseAddress, u32 RegOffset, u64 Data)</a> </dd></dl>

</div>
</div>
<a id="gaa7ede468ba17bf106101d4850184dc74"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa7ede468ba17bf106101d4850184dc74">&#9670;&nbsp;</a></span>XAXIDMA_BUFFLEN_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_BUFFLEN_OFFSET&#160;&#160;&#160;0x00000028</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Tail descriptor pointer. </p>

</div>
</div>
<a id="ga00ee7a235750d8795961223455407051"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga00ee7a235750d8795961223455407051">&#9670;&nbsp;</a></span>XAXIDMA_CDESC_MSB_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_CDESC_MSB_OFFSET&#160;&#160;&#160;0x0000000C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Current descriptor pointer. </p>

</div>
</div>
<a id="ga24b47801eed2ab0ba326b8b40d24f2b1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga24b47801eed2ab0ba326b8b40d24f2b1">&#9670;&nbsp;</a></span>XAXIDMA_CDESC_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_CDESC_OFFSET&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Current descriptor pointer. </p>

</div>
</div>
<a id="ga280fd988ea7ec3fadfe7cf1293f39e36"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga280fd988ea7ec3fadfe7cf1293f39e36">&#9670;&nbsp;</a></span>XAXIDMA_COALESCE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_COALESCE_MASK&#160;&#160;&#160;0x00FF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Coalesce counter. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">XAxiDma_BdRingGetCoalesce()</a>.</p>

</div>
</div>
<a id="ga2d34bf268de2f2ef4d32351043835f68"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga2d34bf268de2f2ef4d32351043835f68">&#9670;&nbsp;</a></span>XAXIDMA_CR_CYCLIC_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_CR_CYCLIC_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Cyclic Mode. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">XAxiDma_SelectCyclicMode()</a>.</p>

</div>
</div>
<a id="ga8bdf83c8ba16d8217a2a6486a9b5b521"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8bdf83c8ba16d8217a2a6486a9b5b521">&#9670;&nbsp;</a></span>XAXIDMA_CR_KEYHOLE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_CR_KEYHOLE_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Keyhole feature. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">XAxiDma_SelectKeyHole()</a>.</p>

</div>
</div>
<a id="ga8534b07ed878f92d2062dc1680fb0391"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8534b07ed878f92d2062dc1680fb0391">&#9670;&nbsp;</a></span>XAXIDMA_CR_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_CR_OFFSET&#160;&#160;&#160;0x00000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Channel control. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">XAxiDma_BdRingGetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">XAxiDma_BdRingSetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>, <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">XAxiDma_SelectCyclicMode()</a>, <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">XAxiDma_SelectKeyHole()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>

</div>
</div>
<a id="ga33fda61f0837d37da36d3b72b90b0fba"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga33fda61f0837d37da36d3b72b90b0fba">&#9670;&nbsp;</a></span>XAXIDMA_CR_RESET_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_CR_RESET_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Reset DMA engine. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, and <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>.</p>

</div>
</div>
<a id="gab0ebdf6b7776e79941efe1325aac5aa9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab0ebdf6b7776e79941efe1325aac5aa9">&#9670;&nbsp;</a></span>XAXIDMA_CR_RUNSTOP_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_CR_RUNSTOP_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Start/stop DMA channel. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>

</div>
</div>
<a id="gae3ad7ae6b5814b99de67bba06ec77ed1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae3ad7ae6b5814b99de67bba06ec77ed1">&#9670;&nbsp;</a></span>XAXIDMA_DELAY_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_DELAY_MASK&#160;&#160;&#160;0xFF000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Delay timeout counter. </p>

</div>
</div>
<a id="ga170ce0e12eb12686a03e006610e2acd2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga170ce0e12eb12686a03e006610e2acd2">&#9670;&nbsp;</a></span>XAXIDMA_DESC_LSB_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_DESC_LSB_MASK&#160;&#160;&#160;(0xFFFFFFC0U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>LSB Address mask. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>

</div>
</div>
<a id="ga3a54e372851dbae81c33997ef2ba8d2f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3a54e372851dbae81c33997ef2ba8d2f">&#9670;&nbsp;</a></span>XAXIDMA_DESTADDR_MSB_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_DESTADDR_MSB_OFFSET&#160;&#160;&#160;0x0000001C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Simple mode destination address pointer. </p>

</div>
</div>
<a id="ga4e98e82ed389c23918315d833b457ea9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4e98e82ed389c23918315d833b457ea9">&#9670;&nbsp;</a></span>XAXIDMA_DESTADDR_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_DESTADDR_OFFSET&#160;&#160;&#160;0x00000018</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Simple mode destination address pointer. </p>

</div>
</div>
<a id="ga4102192c408420feb5b7db14d47c6d5c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4102192c408420feb5b7db14d47c6d5c">&#9670;&nbsp;</a></span>XAXIDMA_ERR_ALL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_ERR_ALL_MASK&#160;&#160;&#160;0x00000770</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>All errors. </p>

</div>
</div>
<a id="gaa19b93d226e97afd08d3869dc530b692"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa19b93d226e97afd08d3869dc530b692">&#9670;&nbsp;</a></span>XAXIDMA_ERR_DECODE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_ERR_DECODE_MASK&#160;&#160;&#160;0x00000040</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Datamover decode err. </p>

</div>
</div>
<a id="ga87ac559811703a8ca33fc6b427913f2b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga87ac559811703a8ca33fc6b427913f2b">&#9670;&nbsp;</a></span>XAXIDMA_ERR_INTERNAL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_ERR_INTERNAL_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Datamover internal err. </p>

</div>
</div>
<a id="ga43ecb16ea8e8d09a33364a17610d8909"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga43ecb16ea8e8d09a33364a17610d8909">&#9670;&nbsp;</a></span>XAXIDMA_ERR_SG_DEC_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_ERR_SG_DEC_MASK&#160;&#160;&#160;0x00000400</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>SG decode err. </p>

</div>
</div>
<a id="ga1f9ef0d10a7456a25a4b244955659d65"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1f9ef0d10a7456a25a4b244955659d65">&#9670;&nbsp;</a></span>XAXIDMA_ERR_SG_INT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_ERR_SG_INT_MASK&#160;&#160;&#160;0x00000100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>SG internal err. </p>

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<a id="ga0f0d25fd68716e868742115c9a28c18c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0f0d25fd68716e868742115c9a28c18c">&#9670;&nbsp;</a></span>XAXIDMA_ERR_SG_SLV_MASK</h2>

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          <td class="memname">#define XAXIDMA_ERR_SG_SLV_MASK&#160;&#160;&#160;0x00000200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>SG slave err. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga6d50743f6c9d6474561f6727eb956915">&#9670;&nbsp;</a></span>XAXIDMA_ERR_SLAVE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_ERR_SLAVE_MASK&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Datamover slave err. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaf03e87b58cf2f9800e6260fda3745631">&#9670;&nbsp;</a></span>XAxiDma_GetRxIndexRing</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_GetRxIndexRing</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RingIndex&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(&amp;((InstancePtr)-&gt;RxBdRing[RingIndex]))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>

<p>Get Receive (Rx) Ring ptr of a Index. </p>
<p>Warning: This has a different API than the LLDMA driver. It now returns the pointer to the BD ring.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on. </td></tr>
    <tr><td class="paramname">RingIndex</td><td>is the channel Index.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Pointer to the Rx Ring</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: <a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * XAxiDma_GetRxIndexRing(<a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> * InstancePtr, int RingIndex) This function is used only when system is configured as SG mode </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga6373ac3baa5365607f6727f4e2ece7a5">&#9670;&nbsp;</a></span>XAxiDma_GetRxRing</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_GetRxRing</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(&amp;((InstancePtr)-&gt;RxBdRing[0]))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>

<p>Get Receive (Rx) Ring ptr. </p>
<p>Warning: This has a different API than the LLDMA driver. It now returns the pointer to the BD ring.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Pointer to the Rx Ring</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: <a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * <a class="el" href="group__axidma__v9__0.html#ga6373ac3baa5365607f6727f4e2ece7a5" title="Get Receive (Rx) Ring ptr. ">XAxiDma_GetRxRing(XAxiDma * InstancePtr)</a> This function is used only when system is configured as SG mode </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>.</p>

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<a id="ga9d91f29c6dc41f2106e097f1f9957a6e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga9d91f29c6dc41f2106e097f1f9957a6e">&#9670;&nbsp;</a></span>XAxiDma_GetTxRing</h2>

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          <td class="memname">#define XAxiDma_GetTxRing</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(&amp;((InstancePtr)-&gt;TxBdRing))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>

<p>Get Transmit (Tx) Ring ptr. </p>
<p>Warning: This has a different API than the LLDMA driver. It now returns the pointer to the BD ring.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Pointer to the Tx Ring</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: <a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e" title="Get Transmit (Tx) Ring ptr. ">XAxiDma_GetTxRing(XAxiDma * InstancePtr)</a> This function is used only when system is configured as SG mode </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, and <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga70671c3d8cd1e51c56723e298d268cce">&#9670;&nbsp;</a></span>XAXIDMA_HALTED_MASK</h2>

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          <td class="memname">#define XAXIDMA_HALTED_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>DMA channel halted. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga18dd03026dd6c0ebd13526116c09ccae">&#9670;&nbsp;</a></span>XAxiDma_HasSg</h2>

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          <td class="memname">#define XAxiDma_HasSg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;((InstancePtr)-&gt;HasSg) ? TRUE : FALSE</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>

<p>This function checks whether system is configured as Simple or Scatter Gather mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE if configured as SG mode</li>
<li>FALSE if configured as simple mode</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, and <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaa3538e8c2a6e024641259c85368667f0">&#9670;&nbsp;</a></span>XAXIDMA_IDLE_MASK</h2>

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      <table class="memname">
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          <td class="memname">#define XAXIDMA_IDLE_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>DMA channel idle. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">XAxiDma_Busy()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga9ff0d2e5b50846e4b6a2d683283c10d5">&#9670;&nbsp;</a></span>XAxiDma_IntrAckIrq</h2>

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          <td class="memname">#define XAxiDma_IntrAckIrq</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Mask, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Direction&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>((InstancePtr)-&gt;RegBase + \</div><div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>, \</div><div class="line">                        (Mask) &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>)</div><div class="ttc" id="group__axidma__v9__0_html_gadfdc083e0b249c04624a66e700d7a7c4"><div class="ttname"><a href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_OFFSET</div><div class="ttdoc">RX channel registers base offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:118</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga73dabf09bac8a209e0cc367f6ccdf44b"><div class="ttname"><a href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:349</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
</div><!-- fragment -->
<p>This function acknowledges the interrupts that are specified in Mask. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on </td></tr>
    <tr><td class="paramname">Mask</td><td>is the mask for the interrupts to be acknowledge </td></tr>
    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
<li>XAXIDMA_DMA_TO_DEVICE.</li>
<li>XAXIDMA_DEVICE_TO_DMA.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga1936b497c0fa61d326807e5ed8dd572b">&#9670;&nbsp;</a></span>XAxiDma_IntrDisable</h2>

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        <tr>
          <td class="memname">#define XAxiDma_IntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Mask, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Direction&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>((InstancePtr)-&gt;RegBase + \</div><div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, \</div><div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((InstancePtr)-&gt;RegBase + \</div><div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>)) \</div><div class="line">                        &amp; ~(Mask &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>))</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gadfdc083e0b249c04624a66e700d7a7c4"><div class="ttname"><a href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_OFFSET</div><div class="ttdoc">RX channel registers base offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:118</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga73dabf09bac8a209e0cc367f6ccdf44b"><div class="ttname"><a href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:349</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
</div><!-- fragment -->
<p>This function disables interrupts specified by the Mask. </p>
<p>Interrupts that are not in the mask are not affected.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on </td></tr>
    <tr><td class="paramname">Mask</td><td>is the mask for the interrupts to be disabled </td></tr>
    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
<li>XAXIDMA_DMA_TO_DEVICE.</li>
<li>XAXIDMA_DEVICE_TO_DMA. </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

</div>
</div>
<a id="gadac28afa26e2cb55bdada1ee3c016c52"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadac28afa26e2cb55bdada1ee3c016c52">&#9670;&nbsp;</a></span>XAxiDma_IntrEnable</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_IntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Mask, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Direction&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>((InstancePtr)-&gt;RegBase + \</div><div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, \</div><div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((InstancePtr)-&gt;RegBase + \</div><div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>)) \</div><div class="line">                        | (Mask &amp; <a class="code" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a>))</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gadfdc083e0b249c04624a66e700d7a7c4"><div class="ttname"><a href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_OFFSET</div><div class="ttdoc">RX channel registers base offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:118</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga73dabf09bac8a209e0cc367f6ccdf44b"><div class="ttname"><a href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a></div><div class="ttdeci">#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Write the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:349</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8347e41a5c01bdabefce9c8484a7ced1"><div class="ttname"><a href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">XAXIDMA_IRQ_ALL_MASK</a></div><div class="ttdeci">#define XAXIDMA_IRQ_ALL_MASK</div><div class="ttdoc">All interrupts. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:194</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
</div><!-- fragment -->
<p>This function enables interrupts specified by the Mask in specified direction, Interrupts that are not in the mask are not affected. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on </td></tr>
    <tr><td class="paramname">Mask</td><td>is the mask for the interrupts to be enabled </td></tr>
    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
<li>XAXIDMA_DMA_TO_DEVICE.</li>
<li>XAXIDMA_DEVICE_TO_DMA. </li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

</div>
</div>
<a id="gadba63ad7c0a784d569736a8d1eb7c367"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadba63ad7c0a784d569736a8d1eb7c367">&#9670;&nbsp;</a></span>XAxiDma_IntrGetEnabled</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_IntrGetEnabled</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Direction&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((InstancePtr)-&gt;RegBase + \</div><div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>) &amp;\</div><div class="line">                                                        XAXIDMA_IRQ_ALL_MASK)</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gadfdc083e0b249c04624a66e700d7a7c4"><div class="ttname"><a href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_OFFSET</div><div class="ttdoc">RX channel registers base offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:118</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga8534b07ed878f92d2062dc1680fb0391"><div class="ttname"><a href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_CR_OFFSET</div><div class="ttdoc">Channel control. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:126</div></div>
</div><!-- fragment -->
<p>This function gets the mask for the interrupts that are currently enabled. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on </td></tr>
    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
<li>XAXIDMA_DMA_TO_DEVICE.</li>
<li>XAXIDMA_DEVICE_TO_DMA.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The bit mask for the interrupts that are currently enabled</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

</div>
</div>
<a id="ga6a0eb17bcfcaf3331e01855d302f5f0e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6a0eb17bcfcaf3331e01855d302f5f0e">&#9670;&nbsp;</a></span>XAxiDma_IntrGetIrq</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_IntrGetIrq</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Direction&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((InstancePtr)-&gt;RegBase + \</div><div class="line">                        (<a class="code" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a> * Direction), <a class="code" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>) &amp;\</div><div class="line">                                                        XAXIDMA_IRQ_ALL_MASK)</div><div class="ttc" id="group__axidma__v9__0_html_gadea426ef26fc5473a78723cd2b92aba5"><div class="ttname"><a href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a></div><div class="ttdeci">#define XAxiDma_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read the given register. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:330</div></div>
<div class="ttc" id="group__axidma__v9__0_html_gadfdc083e0b249c04624a66e700d7a7c4"><div class="ttname"><a href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_RX_OFFSET</div><div class="ttdoc">RX channel registers base offset. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:118</div></div>
<div class="ttc" id="group__axidma__v9__0_html_ga50d6957f8447d4eab9e444666730f692"><div class="ttname"><a href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a></div><div class="ttdeci">#define XAXIDMA_SR_OFFSET</div><div class="ttdoc">Status. </div><div class="ttdef"><b>Definition:</b> xaxidma_hw.h:127</div></div>
</div><!-- fragment -->
<p>This function gets the interrupts that are asserted. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on </td></tr>
    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
<li>XAXIDMA_DMA_TO_DEVICE.</li>
<li>XAXIDMA_DEVICE_TO_DMA.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The bit mask for the interrupts asserted.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

</div>
</div>
<a id="ga8347e41a5c01bdabefce9c8484a7ced1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8347e41a5c01bdabefce9c8484a7ced1">&#9670;&nbsp;</a></span>XAXIDMA_IRQ_ALL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_IRQ_ALL_MASK&#160;&#160;&#160;0x00007000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>All interrupts. </p>

</div>
</div>
<a id="gadc4a45d09bcbf852f29b880935d607dc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadc4a45d09bcbf852f29b880935d607dc">&#9670;&nbsp;</a></span>XAXIDMA_IRQ_DELAY_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_IRQ_DELAY_MASK&#160;&#160;&#160;0x00002000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Delay interrupt. </p>

</div>
</div>
<a id="ga6ceb68e74761910e4253795a9b4992cf"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6ceb68e74761910e4253795a9b4992cf">&#9670;&nbsp;</a></span>XAXIDMA_IRQ_ERROR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_IRQ_ERROR_MASK&#160;&#160;&#160;0x00004000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Error interrupt. </p>

</div>
</div>
<a id="gae420f2ad87e1e00456a6ee3a80d2480d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae420f2ad87e1e00456a6ee3a80d2480d">&#9670;&nbsp;</a></span>XAXIDMA_IRQ_IOC_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_IRQ_IOC_MASK&#160;&#160;&#160;0x00001000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Completion intr. </p>

</div>
</div>
<a id="gaf0f7e862f42d26800868816eea2a949b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf0f7e862f42d26800868816eea2a949b">&#9670;&nbsp;</a></span>XAXIDMA_MICROMODE_MIN_BUF_ALIGN</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_MICROMODE_MIN_BUF_ALIGN&#160;&#160;&#160;0xFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Minimum byte alignment requirement for buffer address in Micro DMA mode. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">XAxiDma_BdSetBufAddrMicroMode()</a>.</p>

</div>
</div>
<a id="gadea426ef26fc5473a78723cd2b92aba5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadea426ef26fc5473a78723cd2b92aba5">&#9670;&nbsp;</a></span>XAxiDma_ReadReg</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAxiDma_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XAxiDma_In32((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Read the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be read</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5" title="Read the given register. ">XAxiDma_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">XAxiDma_BdRingGetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">XAxiDma_BdRingSetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">XAxiDma_Busy()</a>, <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>, <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">XAxiDma_SelectCyclicMode()</a>, <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">XAxiDma_SelectKeyHole()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>

</div>
</div>
<a id="gad80414a88feceb1da4b9f77096d1d590"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad80414a88feceb1da4b9f77096d1d590">&#9670;&nbsp;</a></span>XAXIDMA_RX_CDESC0_MSB_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_RX_CDESC0_MSB_OFFSET&#160;&#160;&#160;0x00000044</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Rx Current Descriptor 0. </p>

</div>
</div>
<a id="ga79d2eca90f2554b8c893b2f9a70c795c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga79d2eca90f2554b8c893b2f9a70c795c">&#9670;&nbsp;</a></span>XAXIDMA_RX_CDESC0_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_RX_CDESC0_OFFSET&#160;&#160;&#160;0x00000040</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Multi-Channel DMA Descriptor Offsets. </p>
<p>Rx Current Descriptor 0 </p>

</div>
</div>
<a id="ga6fc559cbc93b62195de6ecaf25492467"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6fc559cbc93b62195de6ecaf25492467">&#9670;&nbsp;</a></span>XAXIDMA_RX_NDESC_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_RX_NDESC_OFFSET&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Rx Next Descriptor Offset. </p>

</div>
</div>
<a id="gadfdc083e0b249c04624a66e700d7a7c4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadfdc083e0b249c04624a66e700d7a7c4">&#9670;&nbsp;</a></span>XAXIDMA_RX_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XAXIDMA_RX_OFFSET&#160;&#160;&#160;0x00000030</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>RX channel registers base offset. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">XAxiDma_Busy()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">XAxiDma_SelectCyclicMode()</a>, and <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">XAxiDma_SelectKeyHole()</a>.</p>

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<a id="gaa9b5991af857e7bac763311fd917978d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa9b5991af857e7bac763311fd917978d">&#9670;&nbsp;</a></span>XAXIDMA_RX_TDESC0_MSB_OFFSET</h2>

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          <td class="memname">#define XAXIDMA_RX_TDESC0_MSB_OFFSET&#160;&#160;&#160;0x0000004C</td>
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<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Rx Tail Descriptor 0. </p>

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<a id="gadfa4d02f0dd1fd005c695e9977457722"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadfa4d02f0dd1fd005c695e9977457722">&#9670;&nbsp;</a></span>XAXIDMA_RX_TDESC0_OFFSET</h2>

<div class="memitem">
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          <td class="memname">#define XAXIDMA_RX_TDESC0_OFFSET&#160;&#160;&#160;0x00000048</td>
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<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Rx Tail Descriptor 0. </p>

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<a id="gab26580f9b4a94b3ab1d373ddeab7b3b6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab26580f9b4a94b3ab1d373ddeab7b3b6">&#9670;&nbsp;</a></span>XAXIDMA_SGCTL_OFFSET</h2>

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          <td class="memname">#define XAXIDMA_SGCTL_OFFSET&#160;&#160;&#160;0x0000002c</td>
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<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>SG Control Register. </p>

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<a id="ga50d6957f8447d4eab9e444666730f692"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga50d6957f8447d4eab9e444666730f692">&#9670;&nbsp;</a></span>XAXIDMA_SR_OFFSET</h2>

<div class="memitem">
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          <td class="memname">#define XAXIDMA_SR_OFFSET&#160;&#160;&#160;0x00000004</td>
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<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Status. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">XAxiDma_Busy()</a>.</p>

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<a id="gafaafc49751e690d818d604efe368c481"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gafaafc49751e690d818d604efe368c481">&#9670;&nbsp;</a></span>XAXIDMA_SRCADDR_MSB_OFFSET</h2>

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          <td class="memname">#define XAXIDMA_SRCADDR_MSB_OFFSET&#160;&#160;&#160;0x0000001C</td>
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<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Simple mode source address pointer. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga386fad6446792679302b362ed34022cf">&#9670;&nbsp;</a></span>XAXIDMA_SRCADDR_OFFSET</h2>

<div class="memitem">
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          <td class="memname">#define XAXIDMA_SRCADDR_OFFSET&#160;&#160;&#160;0x00000018</td>
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<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Simple mode source address pointer. </p>

</div>
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<a id="ga6063ffb7cb46cdca589e6f31069f7758"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6063ffb7cb46cdca589e6f31069f7758">&#9670;&nbsp;</a></span>XAXIDMA_TDESC_MSB_OFFSET</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XAXIDMA_TDESC_MSB_OFFSET&#160;&#160;&#160;0x00000014</td>
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<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Tail descriptor pointer. </p>

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<a id="gac8626fb2bed7230a2c82a7e1db0ddd35"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac8626fb2bed7230a2c82a7e1db0ddd35">&#9670;&nbsp;</a></span>XAXIDMA_TDESC_OFFSET</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XAXIDMA_TDESC_OFFSET&#160;&#160;&#160;0x00000010</td>
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<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Tail descriptor pointer. </p>

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<a id="ga88232281611059fd669f0339888cd44e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga88232281611059fd669f0339888cd44e">&#9670;&nbsp;</a></span>XAXIDMA_TX_OFFSET</h2>

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          <td class="memname">#define XAXIDMA_TX_OFFSET&#160;&#160;&#160;0x00000000</td>
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<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>TX channel registers base offset. </p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>.</p>

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<a id="ga73dabf09bac8a209e0cc367f6ccdf44b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga73dabf09bac8a209e0cc367f6ccdf44b">&#9670;&nbsp;</a></span>XAxiDma_WriteReg</h2>

<div class="memitem">
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          <td class="memname">#define XAxiDma_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a>&gt;</code></p>

<p>Write the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be written </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b" title="Write the given register. ">XAxiDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">XAxiDma_SelectCyclicMode()</a>, <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">XAxiDma_SelectKeyHole()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>

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<h2 class="groupheader">Typedef Documentation</h2>
<a id="gac08fe7cb6508a133a7ef036bba7df5b5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac08fe7cb6508a133a7ef036bba7df5b5">&#9670;&nbsp;</a></span>XAxiDma</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">typedef struct <a class="el" href="struct_x_axi_dma.html">XAxiDma</a>  <a class="el" href="struct_x_axi_dma.html">XAxiDma</a></td>
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<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>

<p>The <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> driver instance data. </p>
<p>An instance must be allocated for each DMA engine in use. </p>

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<a id="ga5faf4d844b10fc577f3a75a170f11867"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5faf4d844b10fc577f3a75a170f11867">&#9670;&nbsp;</a></span>XAxiDma_Bd</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">typedef u32 XAxiDma_Bd[<a class="el" href="group__axidma__v9__0.html#ga751f6662ab9baed908685eef30d322b8">XAXIDMA_BD_NUM_WORDS</a>]</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bd_8h.html">xaxidma_bd.h</a>&gt;</code></p>

<p>The XAxiDma_Bd is the type for a buffer descriptor (BD). </p>

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<h2 class="groupheader">Function Documentation</h2>
<a id="ga9d2814e4249884e68fe9e6f370920ca4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga9d2814e4249884e68fe9e6f370920ca4">&#9670;&nbsp;</a></span>XAxiDma_BdGetAppWord()</h2>

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          <td class="memname">u32 XAxiDma_BdGetAppWord </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *&#160;</td>
          <td class="paramname"><em>BdPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>Offset</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int *&#160;</td>
          <td class="paramname"><em>Valid</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>

<p>Get the APP word at the specified APP word offset for a BD. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset inside the APP word, it is valid from 0 to 4 </td></tr>
    <tr><td class="paramname">Valid</td><td>is to tell the caller whether parameters are valid</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The APP word. Passed in parameter Valid holds 0 for failure, and 1 for success.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">XAXIDMA_BD_HAS_STSCNTRL_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>.</p>

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<a id="ga44003cd704b7d4868d1dc00bb433a91f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga44003cd704b7d4868d1dc00bb433a91f">&#9670;&nbsp;</a></span>XAxiDma_BdRingAlloc()</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">int XAxiDma_BdRingAlloc </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>NumBd</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> **&#160;</td>
          <td class="paramname"><em>BdSetPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Reserve locations in the BD ring. </p>
<p>The set of returned BDs may be modified in preparation for future DMA transactions. Once the BDs are ready to be submitted to hardware, the application must call <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a> in the same order which they were allocated here. Example:</p>
<pre>
       NumBd = 2;
       Status = XDsma_RingBdAlloc(MyRingPtr, NumBd, &amp;MyBdSet);</pre><pre>       if (Status != XST_SUCCESS)
       {
           // Not enough BDs available for the request
       }</pre><pre>       CurBd = MyBdSet;
       for (i=0; i&lt;NumBd; i++)
       {
           // Prepare CurBd.....</pre><pre>           // Onto next BD
           CurBd = <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745" title="Return the next BD in the ring. ">XAxiDma_BdRingNext(MyRingPtr, CurBd)</a>;
       }</pre><pre>       // Give list to hardware
       Status = XAxiDma_BdRingToHw(MyRingPtr, NumBd, MyBdSet);
</pre><p>A more advanced use of this function may allocate multiple sets of BDs. They must be allocated and given to hardware in the correct sequence: </p><pre>
       // Legal
       XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &amp;MySet1);
       XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);</pre><pre>       // Legal
       XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &amp;MySet1);
       XAxiDma_BdRingAlloc(MyRingPtr, NumBd2, &amp;MySet2);
       XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);
       XAxiDma_BdRingToHw(MyRingPtr, NumBd2, MySet2);</pre><pre>       // Not legal
       XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &amp;MySet1);
       XAxiDma_BdRingAlloc(MyRingPtr, NumBd2, &amp;MySet2);
       XAxiDma_BdRingToHw(MyRingPtr, NumBd2, MySet2);
       XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);
</pre><p>Use the API defined in xaxidmabd.h to modify individual BDs. Traversal of the BD set can be done using <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745" title="Return the next BD in the ring. ">XAxiDma_BdRingNext()</a> and <a class="el" href="group__axidma__v9__0.html#ga86c6d4b9c4f8766634d46a3078eadc8a" title="Return the previous BD in the ring. ">XAxiDma_BdRingPrev()</a>.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
    <tr><td class="paramname">NumBd</td><td>is the number of BDs to allocate </td></tr>
    <tr><td class="paramname">BdSetPtr</td><td>is an output parameter, it points to the first BD available for modification.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the requested number of BDs were returned in the BdSetPtr parameter.</li>
<li>XST_INVALID_PARAM if passed in NumBd is not positive</li>
<li>XST_FAILURE if there were not enough free BDs to satisfy the request.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function should not be preempted by another <a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.</dd></dl>
<p>Do not modify more BDs than the number requested with the NumBd parameter. Doing so will lead to data corruption and system instability.</p>
<p>This function can be used only when DMA is in SG mode </p>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing::FreeCnt</a>, and <a class="el" href="struct_x_axi_dma___bd_ring.html#a3e067ffdf2820a816f2d6dda6e3f9114">XAxiDma_BdRing::FreeHead</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga64cf3c732bc803da742c256ab6372e0e">&#9670;&nbsp;</a></span>XAxiDma_BdRingCheck()</h2>

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          <td class="memname">int XAxiDma_BdRingCheck </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Check the internal data structures of the BD ring for the provided channel. </p>
<p>The following checks are made: </p><pre class="fragment"> - The BD ring is linked correctly in physical address space.
 - The internal pointers point to BDs in the ring.
 - The internal counters add up.
</pre><p>The channel should be stopped (through <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c" title="Pause DMA transactions on both channels. ">XAxiDma_Pause()</a> or <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f" title="Reset both TX and RX channels of a DMA engine. ">XAxiDma_Reset()</a>) prior to calling this function.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if no errors were found.</li>
<li>XST_DMA_SG_NO_LIST if the ring has not been created.</li>
<li>XST_IS_STARTED if the channel is not stopped.</li>
<li>XST_DMA_SG_LIST_ERROR if a problem is found with the internal data structures. If this value is returned, the channel should be reset,and the BD ring should be recreated through <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a> to avoid data corruption or system instability.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing::AllCnt</a>, and <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gad044df5bd676a71226411ba7f78ef20b">&#9670;&nbsp;</a></span>XAxiDma_BdRingClone()</h2>

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          <td class="memname">int XAxiDma_BdRingClone </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *&#160;</td>
          <td class="paramname"><em>SrcBdPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Clone the given BD into every BD in the ring. </p>
<p>Only the fields offset from XAXIDMA_BD_START_CLEAR are copied, for XAXIDMA_BD_BYTES_TO_CLEAR bytes. This covers: BufferAddr, Control/Buffer length, status, APP words 0 - 4, and software ID fields.</p>
<p>This function can be called only when all BDs are in the free group such as immediately after creation of the ring. This prevents modification of BDs while they are in use by hardware or the application.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the BD ring instance to be worked on. </td></tr>
    <tr><td class="paramname">SrcBdPtr</td><td>is the source BD template to be cloned into the list.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the list was modified.</li>
<li>XST_DMA_SG_NO_LIST if a list has not been created.</li>
<li>XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.</li>
<li>XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under hardware or application control.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing::AllCnt</a>, and <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5c6d6f492642dd355478c3a853556d6b">&#9670;&nbsp;</a></span>XAxiDma_BdRingCreate()</h2>

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          <td class="memname">u32 XAxiDma_BdRingCreate </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>PhysAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>VirtAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Alignment</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>BdCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the BD ring instance to be worked on. </td></tr>
    <tr><td class="paramname">PhysAddr</td><td>is the physical base address of application memory region. </td></tr>
    <tr><td class="paramname">VirtAddr</td><td>is the virtual base address of the application memory region.If address translation is not being utilized, then VirtAddr should be equivalent to PhysAddr. </td></tr>
    <tr><td class="paramname">Alignment</td><td>governs the byte alignment of individual BDs. This function will enforce a minimum alignment of XAXIDMA_BD_MINIMUM_ALIGNMENT bytes with no maximum as long as it is specified as a power of 2. </td></tr>
    <tr><td class="paramname">BdCount</td><td>is the number of BDs to setup in the application memory region. It is assumed the region is large enough to contain the BDs.Refer to the "SGDMA Ring Creation" section in <a class="el" href="xaxidma_8h.html">xaxidma.h</a> for more information. The minimum valid value for this parameter is 1.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if initialization was successful<ul>
<li>XST_NO_FEATURE if the provided instance is a non SGDMA type of DMA channel.</li>
</ul>
</li>
<li>XST_INVALID_PARAM under any of the following conditions: 1) BdCount is not positive</li>
</ul>
</dd></dl>
<p>2) PhysAddr and/or VirtAddr are not aligned to the given Alignment parameter;</p>
<p>3) Alignment parameter does not meet minimum requirements or is not a power of 2 value.</p>
<ul>
<li>XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans over address 0x00000000 in virtual address space.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing::AllCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing::FreeCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a7d35cb00bb50fff2e24c15f7d7d8dae0">XAxiDma_BdRing::HasStsCntrlStrm</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ab49406dd2d9ec65e3f38d1cc3c880391">XAxiDma_BdRing::HwCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#afd4e1620895f91a829354e131432d2b3">XAxiDma_BdRing::PostCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing::PreCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#aafd8e01bf65c7950235d8f21cf225e12">XAxiDma_BdRing::Separation</a>, <a class="el" href="group__axidma__v9__0.html#ga932a4ab54f38046e6635b9b87a584c79">XAXIDMA_BD_HAS_DRE_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gac15dd4e956aa14d53a6f92544db468d1">XAXIDMA_BD_HAS_DRE_SHIFT</a>, <a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">XAXIDMA_BD_HAS_STSCNTRL_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga7957d90570574e9c7a7ee308b290ecab">XAXIDMA_BD_MINIMUM_ALIGNMENT</a>, <a class="el" href="group__axidma__v9__0.html#ga730aa200407e3c7e38e6fad914ad1eb0">XAXIDMA_BD_NDESC_MSB_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga64e86b7df328bc7209a28152f86fd609">XAXIDMA_BD_NDESC_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>, and <a class="el" href="group__axidma__v9__0.html#ga170ce0e12eb12686a03e006610e2acd2">XAXIDMA_DESC_LSB_MASK</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaffa661a9a2467c1e274842c147531cea">&#9670;&nbsp;</a></span>XAxiDma_BdRingDumpRegs()</h2>

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          <td class="memname">void XAxiDma_BdRingDumpRegs </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Dump the registers for a channel. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, and <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing::RingIndex</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gad2ac76e5a39486896cd484e51d2898c7">&#9670;&nbsp;</a></span>XAxiDma_BdRingFree()</h2>

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          <td class="memname">int XAxiDma_BdRingFree </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>NumBd</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *&#160;</td>
          <td class="paramname"><em>BdSetPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Frees a set of BDs that had been previously retrieved with <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
    <tr><td class="paramname">NumBd</td><td>is the number of BDs to free. </td></tr>
    <tr><td class="paramname">BdSetPtr</td><td>is the head of a list of BDs returned by <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the set of BDs was freed.</li>
<li>XST_INVALID_PARAM if NumBd is negative</li>
<li>XST_DMA_SG_LIST_ERROR if this function was called out of sequence with <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function should not be preempted by another <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> function call that modifies the BD space. It is the caller's responsibility to ensure mutual exclusion.</dd></dl>
<p>This function can be used only when DMA is in SG mode </p>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing::FreeCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#afd4e1620895f91a829354e131432d2b3">XAxiDma_BdRing::PostCnt</a>, and <a class="el" href="struct_x_axi_dma___bd_ring.html#a92668e60e10a940428e68f816c64eab6">XAxiDma_BdRing::PostHead</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga1e5d328b4d4a247d1530fac3efe4c59c">&#9670;&nbsp;</a></span>XAxiDma_BdRingFromHw()</h2>

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          <td class="memname">int XAxiDma_BdRingFromHw </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>BdLimit</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> **&#160;</td>
          <td class="paramname"><em>BdSetPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Returns a set of BD(s) that have been processed by hardware. </p>
<p>The returned BDs may be examined by the application to determine the outcome of the DMA transactions. Once the BDs have been examined, the application must call <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7" title="Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw(). ">XAxiDma_BdRingFree()</a> in the same order which they were retrieved here.</p>
<p>Example:</p>
<pre>
       NumBd = XAxiDma_BdRingFromHw(MyRingPtr, XAXIDMA_ALL_BDS, &amp;MyBdSet);</pre><pre>       if (NumBd == 0)
       {
          // hardware has nothing ready for us yet
       }</pre><pre>       CurBd = MyBdSet;
       for (i=0; i&lt;NumBd; i++)
       {
          // Examine CurBd for post processing.....</pre><pre>          // Onto next BD
          CurBd = <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745" title="Return the next BD in the ring. ">XAxiDma_BdRingNext(MyRingPtr, CurBd)</a>;
       }</pre><pre>       XAxiDma_BdRingFree(MyRingPtr, NumBd, MyBdSet); // Return the list
</pre><p>A more advanced use of this function may allocate multiple sets of BDs. They must be retrieved from hardware and freed in the correct sequence: </p><pre>
       // Legal
       XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &amp;MySet1);
       XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);</pre><pre>       // Legal
       XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &amp;MySet1);
       XAxiDma_BdRingFromHw(MyRingPtr, NumBd2, &amp;MySet2);
       XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);
       XAxiDma_BdRingFree(MyRingPtr, NumBd2, MySet2);</pre><pre>       // Not legal
       XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &amp;MySet1);
       XAxiDma_BdRingFromHw(MyRingPtr, NumBd2, &amp;MySet2);
       XAxiDma_BdRingFree(MyRingPtr, NumBd2, MySet2);
       XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);
</pre><p>If hardware has partially completed a packet spanning multiple BDs, then none of the BDs for that packet will be included in the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
    <tr><td class="paramname">BdLimit</td><td>is the maximum number of BDs to return in the set. Use XAXIDMA_ALL_BDS to return all BDs that have been processed. </td></tr>
    <tr><td class="paramname">BdSetPtr</td><td>is an output parameter, it points to the first BD available for examination.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The number of BDs processed by hardware. A value of 0 indicates that no data is available. No more than BdLimit BDs will be returned.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Treat BDs returned by this function as read-only. <pre class="fragment">            This function should not be preempted by another XAxiDma ring
    function call that modifies the BD space. It is the caller's
    responsibility to provide a mutual exclusion mechanism.

    This function can be used only when DMA is in SG mode</pre> </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#ab49406dd2d9ec65e3f38d1cc3c880391">XAxiDma_BdRing::HwCnt</a>, and <a class="el" href="struct_x_axi_dma___bd_ring.html#af097be199cf9d1d62cf32f775309a4f3">XAxiDma_BdRing::HwHead</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0d3794bbccf028da8e94407d061dfc68">&#9670;&nbsp;</a></span>XAxiDma_BdRingGetCoalesce()</h2>

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          <td class="memname">void XAxiDma_BdRingGetCoalesce </td>
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          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>CounterPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>TimerPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Retrieve current interrupt coalescing parameters from the given descriptor ring channel. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
    <tr><td class="paramname">CounterPtr</td><td>points to a memory location where the current packet counter will be written. </td></tr>
    <tr><td class="paramname">TimerPtr</td><td>points to a memory location where the current waitbound timer will be written.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The passed in parameters, CounterPtr and TimerPtr, holds the references to the return values.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="group__axidma__v9__0.html#ga280fd988ea7ec3fadfe7cf1293f39e36">XAXIDMA_COALESCE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaaebba5c661e04485582e887e74dbeb94">&#9670;&nbsp;</a></span>XAxiDma_BdRingSetCoalesce()</h2>

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          <td class="memname">int XAxiDma_BdRingSetCoalesce </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Counter</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Timer</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Set interrupt coalescing parameters for the given descriptor ring channel. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
    <tr><td class="paramname">Counter</td><td>sets the packet counter on the channel. Valid range is<ul>
<li>1..255.</li>
<li>XAXIDMA_NO_CHANGE to leave this setting unchanged. </li>
</ul>
</td></tr>
    <tr><td class="paramname">Timer</td><td>sets the waitbound timer on the channel. Valid range is<ul>
<li>0..255.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<ul>
<li>XAXIDMA_NO_CHANGE to leave this setting unchanged. Each unit depend on hardware building parameter C_DLYTMR_RESOLUTION,which is in the range from 0 to 100,000 clock cycles. A value of 0 disables the delay interrupt.</li>
</ul>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if interrupt coalescing settings updated</li>
<li>XST_FAILURE if Counter or Timer parameters are out of range</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaafd18a1df185c30b4745c147e3295ac3">&#9670;&nbsp;</a></span>XAxiDma_BdRingStart()</h2>

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          <td class="memname">int XAxiDma_BdRingStart </td>
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          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em></td><td>)</td>
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<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed. </p>
<p>After a DMA channel is started, it is not halted, and it is idle (no active DMA transfers).</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the Channel instance to be worked on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS upon success</li>
<li>XST_DMA_ERROR if no valid BD available to put into current BD register</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaac81111b373e373be7dd3989fffffe7b">&#9670;&nbsp;</a></span>XAxiDma_BdRingToHw()</h2>

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          <td class="memname">int XAxiDma_BdRingToHw </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>NumBd</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *&#160;</td>
          <td class="paramname"><em>BdSetPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Enqueue a set of BDs to hardware that were previously allocated by <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a>. </p>
<p>Once this function returns, the argument BD set goes under hardware control. Changes to these BDs should be held until they are finished by hardware to avoid data corruption and system instability.</p>
<p>For transmit, the set will be rejected if the last BD of the set does not mark the end of a packet or the first BD does not mark the start of a packet.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
    <tr><td class="paramname">NumBd</td><td>is the number of BDs in the set. </td></tr>
    <tr><td class="paramname">BdSetPtr</td><td>is the first BD of the set to commit to hardware.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the set of BDs was accepted and enqueued to hardware</li>
<li>XST_INVALID_PARAM if passed in NumBd is negative</li>
<li>XST_FAILURE if the set of BDs was rejected because the first BD does not have its start-of-packet bit set, or the last BD does not have its end-of-packet bit set, or any one of the BDs has 0 length.</li>
<li>XST_DMA_SG_LIST_ERROR if this function was called out of sequence with <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a></li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function should not be preempted by another <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> ring function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.</dd></dl>
<p>This function can be used only when DMA is in SG mode </p>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a912bf38e61c8b03995ece842426b3ccf">XAxiDma_BdRing::IsRxChannel</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing::PreCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a8a2958fb6be370d3cc29972f57203952">XAxiDma_BdRing::PreHead</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing::RingIndex</a>, <a class="el" href="group__axidma__v9__0.html#gac279d381208f7f123ac07736702f8ff1">XAXIDMA_BD_CTRL_TXSOF_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">XAXIDMA_BD_STS_COMPLETE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">XAXIDMA_BD_STS_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga495e780d704ecf548d3536b3bb8961a5">XAxiDma_BdGetCtrl</a>, <a class="el" href="group__axidma__v9__0.html#gadaf226acada2c1d857d29205ce4c2a58">XAxiDma_BdGetLength</a>, <a class="el" href="group__axidma__v9__0.html#ga8a0271e5255b139cc63e08e46b9c473a">XAxiDma_BdGetSts</a>, and <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gac58b1ab7a89890142baf67211772d3ce">&#9670;&nbsp;</a></span>XAxiDma_BdRingUnAlloc()</h2>

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          <td class="memname">int XAxiDma_BdRingUnAlloc </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>NumBd</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *&#160;</td>
          <td class="paramname"><em>BdSetPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Fully or partially undo an <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a> operation. </p>
<p>Use this function if all the BDs allocated by <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a> could not be transferred to hardware with <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a>.</p>
<p>This function releases the BDs after they have been allocated but before they have been given to hardware.</p>
<p>This function is not the same as <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7" title="Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw(). ">XAxiDma_BdRingFree()</a>. The Free function returns BDs to the free list after they have been processed by hardware, while UnAlloc returns them before being processed by hardware.</p>
<p>There are two scenarios where this function can be used. Full UnAlloc or Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:</p>
<pre>
   Status = XAxiDma_BdRingAlloc(MyRingPtr, 10, &amp;BdPtr);
       ...
       ...
   if (Error)
   {
       Status = XAxiDma_BdRingUnAlloc(MyRingPtr, 10, &amp;BdPtr);
   }
</pre><p>A partial UnAlloc means some of the BDs Alloc'd will be returned:</p>
<pre>
   Status = XAxiDma_BdRingAlloc(MyRingPtr, 10, &amp;BdPtr);
   BdsLeft = 10;
   CurBdPtr = BdPtr;</pre><pre>   while (BdsLeft)
   {
      if (Error)
      {
         Status = XAxiDma_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr);
      }</pre><pre>      CurBdPtr = <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745" title="Return the next BD in the ring. ">XAxiDma_BdRingNext(MyRingPtr, CurBdPtr)</a>;
      BdsLeft--;
   }
</pre><p>A partial UnAlloc must include the last BD in the list that was Alloc'd.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is a pointer to the descriptor ring instance to be worked on. </td></tr>
    <tr><td class="paramname">NumBd</td><td>is the number of BDs to unallocate </td></tr>
    <tr><td class="paramname">BdSetPtr</td><td>points to the first of the BDs to be returned.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the BDs were unallocated.</li>
<li>XST_INVALID_PARAM if passed in NumBd is negative</li>
<li>XST_FAILURE if NumBd parameter was greater that the number of BDs in the preprocessing state.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function should not be preempted by another <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> ring function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.</dd></dl>
<p>This function can be used only when DMA is in SG mode </p>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing::PreCnt</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gafc6434a23594c20c2b601f010a979e48">&#9670;&nbsp;</a></span>XAxiDma_BdSetAppWord()</h2>

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          <td class="memname">int XAxiDma_BdSetAppWord </td>
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          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *&#160;</td>
          <td class="paramname"><em>BdPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>Offset</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Word</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>

<p>Set the APP word at the specified APP word offset for a BD. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset inside the APP word, it is valid from 0 to 4 </td></tr>
    <tr><td class="paramname">Word</td><td>is the value to set</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS for success</li>
<li>XST_INVALID_PARAM under following error conditions: 1) StsCntrlStrm is not built in hardware 2) Offset is not in valid range</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>If the hardware build has C_SG_USE_STSAPP_LENGTH set to 1, then the last APP word, XAXIDMA_LAST_APPWORD, must have non-zero value when AND with 0x7FFFFF. Not doing so will cause the hardware to stall. This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">XAXIDMA_BD_HAS_STSCNTRL_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gac1a9cb01ba6cd686ee08245f5e08cb22">&#9670;&nbsp;</a></span>XAxiDma_BdSetBufAddr()</h2>

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          <td class="memname">u32 XAxiDma_BdSetBufAddr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *&#160;</td>
          <td class="paramname"><em>BdPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>Addr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>

<p>Set the BD's buffer address. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
    <tr><td class="paramname">Addr</td><td>is the address to set</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if buffer address set successfully</li>
<li>XST_INVALID_PARAM if hardware has no DRE and address is not aligned</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#gad40d36cf3371ad3d176835933dc85e4b">XAXIDMA_BD_HAS_DRE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga932a4ab54f38046e6635b9b87a584c79">XAXIDMA_BD_HAS_DRE_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gafcbd1a131c650a5d6ceee6be15008a77">XAXIDMA_BD_WORDLEN_MASK</a>, and <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga8947514b5acfea6298d0f969f3d2b97e">&#9670;&nbsp;</a></span>XAxiDma_BdSetBufAddrMicroMode()</h2>

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          <td class="memname">u32 XAxiDma_BdSetBufAddrMicroMode </td>
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          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *&#160;</td>
          <td class="paramname"><em>BdPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>Addr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>

<p>Set the BD's buffer address when configured for Micro Mode. </p>
<p>The buffer address should be 4K aligned.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on </td></tr>
    <tr><td class="paramname">Addr</td><td>is the address to set</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if buffer address set successfully</li>
<li>XST_INVALID_PARAM if hardware has no DRE and address is not aligned</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#gaf0f7e862f42d26800868816eea2a949b">XAXIDMA_MICROMODE_MIN_BUF_ALIGN</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga4eb2615ac89054e982c3f3c37f0ddb52">&#9670;&nbsp;</a></span>XAxiDma_BdSetCtrl()</h2>

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          <td class="memname">void XAxiDma_BdSetCtrl </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *&#160;</td>
          <td class="paramname"><em>BdPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>

<p>Set the control bits for a BD. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on. </td></tr>
    <tr><td class="paramname">Data</td><td>is the bit value to set</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#gaa409dba5ec46ad5a31953e22c4d3333f">XAXIDMA_BD_CTRL_ALL_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>, and <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga4056035d8e7c90a68fa954c60d021e07">&#9670;&nbsp;</a></span>XAxiDma_BdSetLength()</h2>

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          <td class="memname">int XAxiDma_BdSetLength </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *&#160;</td>
          <td class="paramname"><em>BdPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>LenBytes</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>LengthMask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>

<p>Set the length field for the given BD. </p>
<p>Length has to be non-zero and less than LengthMask.</p>
<p>For TX channels, the value passed in should be the number of bytes to transmit from the TX buffer associated with the given BD.</p>
<p>For RX channels, the value passed in should be the size of the RX buffer associated with the given BD in bytes. This is to notify the RX channel the capability of the RX buffer to avoid buffer overflow.</p>
<p>The actual receive length can be equal or smaller than the specified length. The actual transfer length will be updated by the hardware in the XAXIDMA_BD_STS_OFFSET word in the BD.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on. </td></tr>
    <tr><td class="paramname">LenBytes</td><td>is the requested transfer length </td></tr>
    <tr><td class="paramname">LengthMask</td><td>is the maximum transfer length</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS for success</li>
<li>XST_INVALID_PARAM for invalid BD length</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">XAXIDMA_BD_CTRL_LEN_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">XAxiDma_BdRead</a>, and <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">XAxiDma_BdWrite</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaff68c0ba3e9e25dfe5e39153301862f8">&#9670;&nbsp;</a></span>XAxiDma_Busy()</h2>

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          <td class="memname">u32 XAxiDma_Busy </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>Direction</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>

<p>This function checks whether specified DMA channel is busy. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on</td></tr>
    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
<li>XAXIDMA_DMA_TO_DEVICE.</li>
<li>XAXIDMA_DEVICE_TO_DMA.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>- TRUE if channel is busy<ul>
<li>FALSE if channel is idle</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#gaa3538e8c2a6e024641259c85368667f0">XAXIDMA_IDLE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>, <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga8026e76c90d891d21c9c355ff776cb77">&#9670;&nbsp;</a></span>XAxiDma_CfgInitialize()</h2>

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          <td class="memname">int XAxiDma_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___config.html">XAxiDma_Config</a> *&#160;</td>
          <td class="paramname"><em>Config</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>

<p>This function initializes a DMA engine. </p>
<p>This function must be called prior to using a DMA engine. Initializing a engine includes setting up the register base address, setting up the instance data, and ensuring the hardware is in a quiescent state.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on. </td></tr>
    <tr><td class="paramname">Config</td><td>is a pointer to an <a class="el" href="struct_x_axi_dma___config.html" title="The configuration structure for AXI DMA engine. ">XAxiDma_Config</a> structure. It contains the information about the hardware build, including base address,and whether status control stream (StsCntrlStrm), MM2S and S2MM are included in the build.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS for successful initialization</li>
<li>XST_INVALID_PARAM if pointer to the configuration structure is NULL</li>
<li>XST_DMA_ERROR if reset operation failed at the end of initialization</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>We assume the hardware building tool will check and error out for a hardware build that has no transfer channels. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma.html#a663f5757eabe6b1b8813ed5fdb0d0edb">XAxiDma::AddrWidth</a>, and <a class="el" href="struct_x_axi_dma___config.html#a6fc1c26fb40944182ff84e370e667eb0">XAxiDma_Config::AddrWidth</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga53983f629aba5b4ebf27f803a7a9284e">&#9670;&nbsp;</a></span>XAxiDma_DumpBd()</h2>

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          <td class="memname">void XAxiDma_DumpBd </td>
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          <td class="paramtype"><a class="el" href="group__axidma__v9__0.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *&#160;</td>
          <td class="paramname"><em>BdPtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xaxidma__bd_8c.html">xaxidma_bd.c</a>&gt;</code></p>

<p>Dump the fields of a BD. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BdPtr</td><td>is the BD to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0cbcf5259635ea3c336fe5413c98f75c">&#9670;&nbsp;</a></span>XAxiDma_LookupConfig()</h2>

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          <td class="memname"><a class="el" href="struct_x_axi_dma___config.html">XAxiDma_Config</a> * XAxiDma_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
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<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>

<p>Look up the hardware configuration for a device instance. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique device ID of the device to lookup for</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The configuration structure for the device. If the device ID is not found,a NULL pointer is returned.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gadb572b623215a7df62b1e0468e3bd68c">&#9670;&nbsp;</a></span>XAxiDma_Pause()</h2>

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          <td class="memname">int XAxiDma_Pause </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>

<p>Pause DMA transactions on both channels. </p>
<p>If the engine is running and doing transfers, this function does not stop the DMA transactions immediately, because then hardware will throw away our previously queued transfers. All submitted transfers will finish. Transfers submitted after this function will not start until <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a> or <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574" title="Resume DMA transactions on both channels. ">XAxiDma_Resume()</a> is called.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if successful</li>
<li>XST_NOT_SGDMA, if the driver instance is not initialized</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gab0ebdf6b7776e79941efe1325aac5aa9">XAXIDMA_CR_RUNSTOP_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">XAxiDma_GetTxRing</a>, <a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">XAxiDma_HasSg</a>, <a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>, and <a class="el" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5b7d1248ef065915fd8c9e8d5e00640f">&#9670;&nbsp;</a></span>XAxiDma_Reset()</h2>

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          <td class="memname">void XAxiDma_Reset </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>

<p>Reset both TX and RX channels of a DMA engine. </p>
<p>Reset one channel resets the whole AXI DMA engine.</p>
<p>Any DMA transaction in progress will finish gracefully before engine starts reset. Any other transactions that have been submitted to hardware will be discarded by the hardware.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>After the reset:<ul>
<li>All interrupts are disabled.</li>
<li>Engine is halted </li>
</ul>
</dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="group__axidma__v9__0.html#ga0d79253861939c76e6d440ecde2b6edd">XAxiDma_BdRingSnapShotCurrBd</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga33fda61f0837d37da36d3b72b90b0fba">XAXIDMA_CR_RESET_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gaf03e87b58cf2f9800e6260fda3745631">XAxiDma_GetRxIndexRing</a>, <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">XAxiDma_GetTxRing</a>, <a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">XAxiDma_HasSg</a>, <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga88232281611059fd669f0339888cd44e">XAXIDMA_TX_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gad4ea3039216916336ae1c7598ff26afc">XAxiDma_Selftest()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaf73e1329e40c8ac1ae47a7d9c104af75">&#9670;&nbsp;</a></span>XAxiDma_ResetIsDone()</h2>

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          <td class="memname">int XAxiDma_ResetIsDone </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>

<p>Check whether reset is done. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>1 if reset is done.</li>
</ul>
</dd></dl>
<ul>
<li>0 if reset is not done</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#ga33fda61f0837d37da36d3b72b90b0fba">XAXIDMA_CR_RESET_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga6373ac3baa5365607f6727f4e2ece7a5">XAxiDma_GetRxRing</a>, <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">XAxiDma_GetTxRing</a>, and <a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga847cd9a0255fcb444bce58b945de8574">&#9670;&nbsp;</a></span>XAxiDma_Resume()</h2>

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          <td class="memname">int XAxiDma_Resume </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>

<p>Resume DMA transactions on both channels. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the DMA engine instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS for success</li>
<li>XST_NOT_SGDMA if the driver instance has not been initialized</li>
<li>XST_DMA_ERROR if one of the channels fails to start</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">&#9670;&nbsp;</a></span>XAxiDma_SelectCyclicMode()</h2>

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          <td class="memname">int XAxiDma_SelectCyclicMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>Direction</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>Select</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>

<p>This function Enable or Disable Cyclic Mode Feature. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on</td></tr>
    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
<li>XAXIDMA_DMA_TO_DEVICE.</li>
<li>XAXIDMA_DEVICE_TO_DMA.  Select is the option to enable (TRUE) or disable (FALSE).</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>- XST_SUCCESS for success</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#ga2d34bf268de2f2ef4d32351043835f68">XAXIDMA_CR_CYCLIC_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>, <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5becc8b0f9945af34e372ced2b37aebb">&#9670;&nbsp;</a></span>XAxiDma_SelectKeyHole()</h2>

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          <td class="memname">int XAxiDma_SelectKeyHole </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>Direction</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>Select</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>

<p>This function Enable or Disable KeyHole Feature. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the driver instance we are working on</td></tr>
    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
<li>XAXIDMA_DMA_TO_DEVICE.</li>
<li>XAXIDMA_DEVICE_TO_DMA.  Select is the option to enable (TRUE) or disable (FALSE).</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>- XST_SUCCESS for success</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#ga8bdf83c8ba16d8217a2a6486a9b5b521">XAXIDMA_CR_KEYHOLE_MASK</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>, <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">XAXIDMA_RX_OFFSET</a>, and <a class="el" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gad4ea3039216916336ae1c7598ff26afc">&#9670;&nbsp;</a></span>XAxiDma_Selftest()</h2>

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          <td class="memname">int XAxiDma_Selftest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma_8h.html">xaxidma.h</a>&gt;</code></p>

<p>Runs a self-test on the driver/device. </p>
<p>This test perform a reset of the DMA device and checks the device is coming out of reset or not</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if self-test was successful</li>
</ul>
</dd></dl>
<ul>
<li>XST_FAILURE if the device is not coming out of reset.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga32ca6099d7926297a4c17cdb4a19511b">&#9670;&nbsp;</a></span>XAxiDma_SimpleTransfer()</h2>

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          <td class="memname">u32 XAxiDma_SimpleTransfer </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BuffAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Length</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>Direction</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xaxidma_8c.html">xaxidma.c</a>&gt;</code></p>

<p>This function does one simple transfer submission. </p>
<p>It checks in the following sequence:</p><ul>
<li>if engine is busy, cannot submit</li>
<li>if engine is in SG mode , cannot submit</li>
</ul>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the pointer to the driver instance </td></tr>
    <tr><td class="paramname">BuffAddr</td><td>is the address of the source/destination buffer </td></tr>
    <tr><td class="paramname">Length</td><td>is the length of the transfer </td></tr>
    <tr><td class="paramname">Direction</td><td>is DMA transfer direction, valid values are<ul>
<li>XAXIDMA_DMA_TO_DEVICE.</li>
<li>XAXIDMA_DEVICE_TO_DMA.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS for success of submission</li>
<li>XST_FAILURE for submission failure, maybe caused by: Another simple transfer is still going</li>
<li>XST_INVALID_PARAM if:Length out of valid range [1:8M] Or, address not aligned when DRE is not built in</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is used only when system is configured as Simple mode. </dd></dl>

<p class="reference">References <a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">XAxiDma_HasSg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga7b38bc9220c391823219937580bd816f">&#9670;&nbsp;</a></span>XAxiDma_StartBdRingHw()</h2>

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          <td class="memname">int XAxiDma_StartBdRingHw </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed. </p>
<p>After a DMA channel is started, it is not halted, and it is idle (no active DMA transfers).</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the Channel instance to be worked on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS upon success</li>
<li>XST_DMA_ERROR if no valid BD available to put into current BD register</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing::ChanBase</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing::RingIndex</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>, <a class="el" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">XAxiDma_BdRingHwIsStarted</a>, <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">XAXIDMA_CR_OFFSET</a>, <a class="el" href="group__axidma__v9__0.html#gab0ebdf6b7776e79941efe1325aac5aa9">XAXIDMA_CR_RUNSTOP_MASK</a>, <a class="el" href="group__axidma__v9__0.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>, and <a class="el" href="group__axidma__v9__0.html#ga73dabf09bac8a209e0cc367f6ccdf44b">XAxiDma_WriteReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3">XAxiDma_BdRingStart()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga39ee7d89e4453276d615849acad27fde">&#9670;&nbsp;</a></span>XAxiDma_UpdateBdRingCDesc()</h2>

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          <td class="memname">int XAxiDma_UpdateBdRingCDesc </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *&#160;</td>
          <td class="paramname"><em>RingPtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xaxidma__bdring_8c.html">xaxidma_bdring.c</a>&gt;</code></p>

<p>Update Current Descriptor. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">RingPtr</td><td>is the Channel instance to be worked on</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS upon success</li>
<li>XST_DMA_ERROR if no valid BD available to put into current BD register</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function can be used only when DMA is in SG mode </dd></dl>

<p class="reference">References <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing::AllCnt</a>, <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing::RingIndex</a>, and <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing::RunState</a>.</p>

<p class="reference">Referenced by <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3">XAxiDma_BdRingStart()</a>.</p>

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